Low Power V.32 bis Modem
CMX869
6.
C-BUS Interface and Software Description
This block provides for the transfer of data and control or status information between the CMX869’s
internal registers and the µC over the C-BUS serial bus. Each transaction consists of a single Register
Address byte sent from the µC which may be followed by one or more data bytes sent from the µC to be
written into one of the CMX869’s Write Only Registers, or one or more bytes of data read out from one of
the CMX869’s Read Only Registers, as illustrated in Figure 8.
Data sent from the µC on the Command Data line is clocked into the CMX869 on the rising edge of the
Serial Clock input. Reply Data sent from the CMX869 to the µC is valid when the Serial Clock is high. The
CSN line must be held low during a data transfer and kept high between transfers. The C-BUS interface is
compatible with most common µC serial interfaces and may also be easily implemented with general
purpose µC I/O pins controlled by a simple software routine. Figure 13 gives detailed C-BUS timing
requirements.
The following C-BUS addresses and registers are used by the CMX869:
General Reset Command (address only, no data).
General Control Register, 16-bit write only.
Transmit Mode Register, 16-bit write-only.
Receive Mode Register, 16-bit write-only.
Transmit Data Register, 8 or 16-bit write only.
Alternate Transmit Data Register, 8-bit write only.
Receive Data Register, 8 or 16-bit read-only.
Status Register, 16-bit read-only.
Address $01
Address $E0
Address $E1
Address $E2
Address $E3
Address $E4
Address $E5
Address $E6
Address $E8
Address $EA
Address $EB
Programming Register, 16-bit write-only.
QAM Modem Command Register, 16-bit write-only.
QAM Modem Status Register, 16-bit read-only.
Note: The C-BUS addresses $E7, $E9, $EC, $ED, $EE and $EF are allocated for production testing and
should not be accessed in normal operation.
Interrupt Operation
The CMX869 will issue an interrupt, by taking the IRQN line low, when the IRQ bit 15 of the Status
Register and the IRQ Enable bit 6 in the General Control Register are both set = 1. The IRQ bit operation
is described in section 6.8.
© 2004 CML Microsystems Plc
18
D/869/4
CMLMICRO [ CML MICROCIRCUITS ]
