Low Power V.32 bis Modem
CMX869
General Control Register b9: Relay Drive
This bit directly controls the RDRVN output pin.
b9 = 1
b9 = 0
RDRVN output pin pulled to VSS
RDRVN output pin pulled to VDD
General Control Register b8: Power-up
This bit controls the internal power supply to most of the internal circuits, including the Xtal
oscillator, internal clock synthesizer and VBIAS supply. Note that the General Reset command
clears this bit, putting the device into Powersave mode.
b8 = 1
b8 = 0
Device powered up normally
Powersave mode (all circuits disabled, except the on-chip regulator,
Ring Detect, RDRVN and C-BUS interface)
When power is first applied to the device, the following power-up procedure should be followed
to ensure correct operation.
i.
(Power is applied to the device)
ii.
iii.
Issue a General Reset command.
Write to the General Control Register (address $E0 setting both the Power-up bit
(b8) and the reset bit (b7) to 1 – leave in this state for a minimum of about 20ms –
this is required to ensure that the crystal oscillator, on-chip regulator and the VBIAS
supply are all operating prior to running any transmit or receive functions
The device is now ready to be programmed as and when required. Examples:
iv.
•
A General Reset command could be issued to clear all the registers and
therefore powersave the device.
•
The Reset bit in the General Control Register could be set to 0 as part of a
routine to program all the relevant registers for setting up a particular operating
mode.
When the device is switched from Powersave mode to normal operation by setting the Power-up
bit to 1, the Reset bit should also be set to 1 and should be held at 1 for about 20ms while the
on-chip regulator, crystal oscillator, clock synthesizer and VBIAS stabilise before starting to use
the transmitter or receiver.
General Control Register b7: Reset
Setting this bit to 1 resets the CMX869’s internal circuitry, clearing all bits of the Transmit Mode,
Receive Mode, QAM Modem Control and Programming Registers and b13-0 of the Status
Register.
b7 = 1
b7 = 0
Internal circuitry in a reset condition.
Normal operation
General Control Register b6: IRQNEN (IRQN O/P Enable)
Setting this bit to 1 enables the IRQN output pin.
b6 = 1
b6 = 0
IRQN pin driven low (to VSS) if the IRQ bit of the Status Register = 1
IRQN pin disabled (high impedance)
General Control Register b5-0: IRQ Mask bits
These bits affect the operation of the IRQ bit of the Status Register as described in section 6.8
© 2004 CML Microsystems Plc
21
D/869/4
CMLMICRO [ CML MICROCIRCUITS ]
