CMX7164 Multi Mode Modem
CMX7164
16/17
14/15
21/10/13
01/08/13
Update of graphs to improve datasheet clarity in v14. Datasheet becomes v16.
Added details of FI-2 Equaliser operation
Added programming register control for I/Q dc offset acquisition
Added corrections to framesync programming register description
Added power connection to pin 37 in Figure 7
Enhancements for custom filter support
Added payload byte lengths to Tables 3, 4, 5 and 6
Document formatting corrected and typos/clarifications
Added RD-LAP channel coding block types in FI-2.x
Clarification of FI-1.x channel coding
11/12/
13
10
15/03/13
10/01/13
30/4/12
9/1/12
Add 8-FSK and 16-FSK operation in FI-2.x
9
Add GMSK/GFSK operation in FI-1.x
8
Added details of FI-4 Equaliser operation and control: Mode register,
programming block
Added details of programming block read mechanism (Available for selected
programming registers only)
Updated receive performance curves for FI-4
Added description of soft decision output bits for FI-2 only
Added details of bus hold function for unused inputs
Added details of Core regulator select
Corrected conditions under which current measurements were made
Changed reference to input impedance of I/Q INPUTs
Typos/clarifications
7
21/09/11
Remove constraint on use of document with FI-2.x, as the latter is now
updated.
6
5
4
22/08/11
17/8/11
3/8/11
Advice in section 5.5 greyed out as not implemented in current FI.
Added advice about terminating unconnected GPIO pins in section 5.5
Added details of default and inverting gains to the description of the I/Q Output
Control - $5D, $5E registers
Pointed out correct use of handshaking when using signal control (Register
$61) to select I and Q offset measurements (Registers $75 and $76)
Clarified behaviour of the I and Q offset registers (Rx dc offset correction) when
using automatic Rx IQ dc mode
Clarified behaviour and scaling of RSSI measurements
Documented further AGC controls added in FI-4.0.5.4, and described AGC
operation in detail
Documented the Pll On bit added to the mode register in FI-4.0.5.4, which
provides a fast idle mode for programming register modifications without
powersave, but with improved speed
Added parameters in Program Block 1 to reduce delay when transitioning from
Idle to Tx or Rx modes
Added information about receive dynamic range
Corrected and clarified scaling of Tx output fine control.
2015 CML Microsystems Plc
Page 11
D/7164_FI-1.x/FI-2.x/FI-4.x/FI-6.x/22
CMLMICRO [ CML MICROCIRCUITS ]
