CMX7164 Multi Mode Modem
CMX7164
1.1 History
Version Changes
Date
(D/M/Y)
22
11/05/15
Added information covering 7164FI-6.x
Section 7.4.22: AGC control algorithm can now be used to control a second
device using one of the available GPIO pins.
Section 10.1 Updated Figure 82 (QAM Mappings)
Section 12.2: Original C-BUS timing diagram replaced by latest version
Section 13.1.22:Register $B3 – changed reserved bit 9 set value and added
example settings
Section 13.1.31: description for register $77: b11-0 description corrected to
describe RSSI averaging period set by P4.3
Section 13.2.6 (Prog Block 4 – Modulation Control): P4.5 entry corrected to
indicate that the parameter also supports FI-1.x
Section 13.2.6: Added description for P4.3
Section 13.2.7: Transmit sequence – added description for minimum pulse
period on GPIOA to trigger transmission and corrected the explanation of DC
Calibration Sequence delays for default values
Descriptions for registers $5D, $5E, $5F, $60, $61, $65 – added note
regarding delay between successive writes
Section 13.2.9: Added Program Block 7.17 for AGC control of external device
via GPIO pins.
Section 15.10: App Note updated for clarification
Section 12: Performance figures replace TBDs
Section 13.1.22: $B3 register table corrected and note added describing
correct settings for the I/Q output drivers
21
02/09/14
Section 13.2.2: Table for P0.0, b11-0 corrected to show value of 1 as invalid
Section 13.2.5: Table showing new program registers P3.3 to P3.6 and
associated description
Section 13.2.6: Summary table, and subsequent description, Program Block 4,
P4.5 corrected to say that two of the values apply also to FI-1.x.
Section 13.2.6: Summary table for Program Block 4, P4.8:b15-2 corrected to
say “reserved, set to 1”
Section 15.10: New Application Note - Aborting Rx and Restarting Frame Sync
Search
Miscellaneous typographical and editorial improvements
Section 13.2.4: Clarification to description on frame sync detection and error
tolerance.
20
19/06/14
Section 13.2.6: Entries and descriptions for P4.8 to P4.10 which offer
additional control
19
18
12/05/14
12/02/14
Added 16-FSK operation
Section 11: Performance figures replace TBDs
Section 12.2.4: Entire section rewritten to improve clarity
Described the state of GPIO pins after reset and before a Function Image is
loaded
Added voltage differential between power supplies to section 11 specification
Added description of RAMDAC ramp profile scaling
Added description of modulation envelope ramp control
Added control method for narrower channel filter options in FI-1.x
Added information on 8/16 FSK, channel coding
Figure 5 replaced by new drawing showing removal of unused components
Miscellaneous typographical and editorial improvements
2015 CML Microsystems Plc
Page 10
D/7164_FI-1.x/FI-2.x/FI-4.x/FI-6.x/22
CMLMICRO [ CML MICROCIRCUITS ]
