CMX7163 QAM Modem
CMX7163
1.1
History
Changes
Section 10.2.6: Entries and descriptions for P4.8 to P4.10 which offer additional
control
Section 10.2.4: Clarification to description of frame sync detection and error
tolerance
Figure 5 replaced by new drawing showing removal of unused components
Described the state of GPIO pins after reset and before a Function Image is
loaded
Added voltage differential between power supplies to section 11 specification
Added details of RAMDAC ramp profile scaling control
Clarified PLL Lock time/Ref divide register
Miscellaneous typographical and editorial improvements
Added details of Equaliser operation and control: Mode register, programming
block
Added details of programming block read mechanism (Available for selected
programming registers only)
Updated receive performance curves
Added details of bus hold function for unused inputs
Added details of Core regulator select
Corrected conditions under which current measurements were made
Changed reference to input impedance of I,QINPUTs
Typos/clarifications
Advice in section 5.5 greyed out as not implemented in current FI.
Added advice about terminating unconnected GPIO pins in section 5.5
Added details of default and inverting gains to the description of the I Q Output
Control - $5D, $5E registers
Pointed out correct use of handshaking when using signal control (Register
$61) to select I and Q offset measurements (Registers $75 and $76)
Clarified behaviour of the I and Q offset registers (Rx dc offset correction)
when using automatic Rx IQ dc mode
Clarified behaviour and scaling of RSSI measurements
Documented further AGC controls added in FI-4.0.5.4, and described AGC
operation in detail
Documented the Pll On bit added to the mode register in FI-4.0.5.4, which
provides a fast idle mode for programming register modifications without
powersave, but with improved speed
Added parameters in Program Block 1 to reduce delay when transitioning from
Idle to Tx or Rx modes
Added information about receive dynamic range
Corrected and clarified scaling of Tx output fine control.
Date
(D/M/Y)
19/6/14
Version
12
11
6/2/14
10
6/1/12
9
8
7
22/08/11
17/8/11
3/8/11
2014 CML Microsystems Plc
Page 6
D/7163_FI-4.x/12
CMLMICRO [ CML MICROCIRCUITS ]
