CMX7163 QAM Modem
CMX7163
10.1.24 VBIAS Control - $B7 write.
7.4.20 Auxiliary DAC/RAMDAC Operation
The four auxiliary DACs are programmed via the AuxDAC1-4 Control - $59 to $5C write registers.
AuxDAC1 may also be programmed to operate as a RAMDAC which will autonomously output a pre-
programmed profile at a programmed rate. The RAMDAC may be configured as automatic or manual
using
P4.8: Set legacy timing mode
b0
b1
ADC Sample
Delay
0 - minimal delay mode (gives a delay of 1.2 symbol times)
1 - legacy delay mode (gives a delay of 8.2 symbol times)
Tx Done and
Tx Last Tail
indication
timing
0-Selects minimal jitter of +/-0.6 symbol times for Tx Done and Tx Last Tail
indication timing.
Enables the use of the P4.9 delay adjustment control for Tx Done and Tx
Last Tail indication timing. Adjusting these delays enables indication timing to
be changed to better match any changes in Tx pulse shaping filter delay or
for other user purposes.
1-legacy timing delay mode (delay not specified; delay and jitter behaviours will
be consistent so long as the number of data field symbols, number of tail
symbols, and other factors are not changed)
b2-15
Reserved
Reserved – set to 1
P4.9: Set Tx Done delay
Only if P4.8 b1=0 then this controls the delay in indicating Tx Done and Tx Last Tail indications, in units of
1.2 symbol times. The default value makes Tx Done indication coincide with when the end of the last data
field symbol analog signal is produced at the CMX7164 IOUTPUT and QOUTPUT pins when the default
Tx pulse shaping filter is engaged. The user may adjust this parameter value to suit the different delay of
any other different pulse shaping filter used.
P4.10: Offset tx end sequence start time
Adjusts the tx end sequence start time to be earlier than the default time. Adjustment is in symbols.
Program Block 5 – Burst Tx Sequence. The AuxDAC1-4 Control - $59 to $5C write register, with b12 set,
controls the RAMDAC mode of operation when configured as a manually triggered RAMDAC. The
RAMDAC ramp rate is controlled by the Internal system clock rate, which changes between active
CS/Tx/Rx modes and Idle mode. Therefore it is inadvisable to return to Idle mode prior to RAMDAC ramp
completion.
The default profile is a Raised Cosine (see Table 7 in the user manual), but this may be over-written with a
user defined profile by writing to Program Block 0. The current profile may be scaled using the Signal
Control - $61 write register. The AuxDAC outputs hold the user-programmed level during a powersave
operation if left enabled, otherwise they will return to zero.
See:
10.1.7 AuxDAC1-4 Control - $59 to $5C write
10.2.2 Program Block 0 – RAMDAC
10.2.3 Program Block 1 – Clock Control
0
P4.8: Set legacy timing mode
2014 CML Microsystems Plc
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