Digital PMR Radio Processor
CMX7131/CMX7141
3
Signal List
CMX7141
48-pin
Q3/L4
Pin
Name
Type
Description
C-BUS: A 'wire-ORable' output for connection to the Interrupt
Request input of the host. Pulled down to DV
SS
when active
and is high impedance when inactive. An external pull-up
resistor (R1) is required.
RF Synthesiser 1 negative input
RF Synthesiser 1 positive input
The negative supply rail (ground) for RF Synthesiser 1
RF Synthesiser 1 Charge Pump output
RF Synthesiser 1 Charge Pump Current Set input
The 2.5V positive supply rail for both RF Synthesisers. This
should be decoupled to RFV
SS
by a capacitor mounted
close to the device pins.
RF Synthesiser 2 negative input
RF Synthesiser 2 positive input
The negative supply rail (ground) for RF Synthesiser 2
RF Synthesiser 2 Charge Pump output
RF Synthesiser 2 Charge Pump Current Set input
The 3.3V positive supply rail for the RF Synthesiser charge
pumps. This should be decoupled to RFV
SS
by a capacitor
mounted close to the device pins.
RF Clock Input (common to both RF Synthesisers)
1
General purpose I/O pin
General purpose I/O pin
Reserved – do not connect this pin
Internally generated 2.5V digital supply voltage. Must be
decoupled to DV
SS
by capacitors mounted close to the
device pins. No other connections allowed, except for
optional connection to RFV
DD
.
Rx Enable – active low when in Rx mode ($C1:b0 = 1)
Synthesised Digital System Clock Output 1
Digital ground
Reserved – do not connect this pin
Tx Enable – active low when in Tx mode ($C1:b1 = 1)
Discriminator inverting input
Discriminator input amplifier feedback
Alternate inverting input
CMX7131
64-pin
Q1/L9
1
8
IRQN
OP
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
-
-
-
-
-
-
-
-
-
-
-
-
-
11
12
-
RF1N
RF1P
RFVSS
CP1OUT
ISET1
RFVDD
RF2N
RF2P
RFVSS
CP2OUT
ISET2
CPVDD
RFCLK
GPIOA
GPIOB
-
IP
IP
PWR
OP
IP
PWR
IP
IP
PWR
OP
IP
PWR
IP
OP
OP
NC
18
9
VDEC
PWR
19
20
21
22
23
24
25
26
10
13
14
-
15
16
17
18
RXENA
SYSCLK1
DVSS
-
TXENA
DISC
DISCFB
ALT
OP
OP
PWR
NC
OP
IP
OP
IP
1
To minimise crosstalk, this signal should be connected to the same clock source as XTAL/CLK input.
2014 CML Microsystems Plc
Page 8
D/7141_FI-3.x/6
CMLMICRO [ CML MICROCIRCUITS ]
