Digital PMR Radio Processor
CMX7131/CMX7141
5.3.2 Internal Processing
The CMX7131/CMX7141 operates as a half-duplex device, either receiving signals from the RF circuits in
Rx mode, or sourcing signals to the RF circuits in Tx mode. It also has a low power IDLE mode to support
battery saving protocols. The internal data processing blocks for Tx and Rx modes are illustrated in Figure
12. Additional processing in I/Q Mode is shown in Figure 13.
Frame
Type
Detect
FEC
Interleave
Scramble
C-BUS
Port
Packet
Formatter
Data Buffer
I/Q
Look-up
MOD1 out
MOD2 out
Data
Router
4-FSK
Modulator
Filter
Mux
Control info
SPI Port
(from AMBE-
3000)
Voice data
DISC input
Voice data
SPI Port
Frame
Type
Detect
De-interleave
De-scramble
De-FEC
(to vocoder)
4-FSK
Demod
Packet De-
formatter
Filter
Data
Router
Control info
Address
Matcher
AFSD
C-BUS
Port
Data Buffer
Figure 12 Internal Data Blocks (LD Mode)
Power Save
C-BUS
Control of
CMX994
C-BUS
Input 1
(I)
Freq
Offset
Frequency
Offset
RSSI 1
RSSI 1
RSSI 2
RSSI 2
DC
offset
control
Inverse
TAN
To
demodulation
blocks
Input 2
(Q)
RSSI
AGC
Figure 13 Additional Internal Data Processing in I/Q Mode
5.3.3 Frame Sync Detection and Demodulation
The analogue signal from the receiver may be from either a CMX994 I/Q interface or a limiter/discriminator
(LD) output. The signal(s) from the RF section should be applied to the CMX7131/CMX7141 input(s)
(normally the DISC input for LD Rx and DISC and ALT inputs for I/Q Rx). The signals can be adjusted to
the correct level either by selection of the feedback resistor(s) or using the CMX7131/CMX7141 Input Gain
2014 CML Microsystems Plc
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