Digital PMR Radio Processor
CMX7131/CMX7141
5.2.4 Serial Memory Connection (LD Mode only)
In all cases, the auxiliary C-BUS/SPI-Codec bus is shared with the serial memory bus which may be used
to load the contents of the Function Image. Bus conflicts are avoided by the use of an additional Chip
Select signal (SSOUT). If this feature is not used then the EPSCSN pin should be left un-connected. Serial
Memory may not be used in I/Q interface mode.
5.2.5 CMX994 Connection (I/Q Mode only)
The CMX994 can be connected via the C-BUS connection in place of the serial memory (Table 4). This
allows the CMX994 to be used along with the AMBE-3000TM Vocoder.
Note that the data and clock connections to the CMX994 are common with the Vocoder, so the data traffic
on the interface is a potential source of noise/interference in the radio.
Table 4 CMX994 Connections
CMX7131/CMX7141 Pin:
EPSCSN
CMX994 Pin:
CSN
EPSI
EPSCLK
CDATA
SCLK
No connection
RDATA
The operation of the CMX994 is generally automatic, however specific data may be written to CMX994
registers using the pass-through mode available using register $C8. For example if the CMX994 PLL and
VCO are used in the radio design then it is necessary to programme the appropriate frequency data to the
CMX994 PLL-M Divider, PLL N-Divider and VCO Control registers using the pass-through mode before
attempting reception.
5.2.6 Hardware AGC – AuxADC1 Connection
In I/Q mode, the AuxADC1 input can be used to improve the adjacent/alternate channel rejection with the
addition of suitable external components, see Figure 6. This function provides a broadband signal detector
which is used in the AGC process. This is required to prevent the DISC/ALT ADC inputs limiting internally
in the presence of alternate channel signals, which are attenuated by the inherent filtering of the ADC.
This functionality is enabled by setting:
Program Block P2.0:b8=1 (enable hardware AGC)
Program Block P3.0 = $F002 (AuxADC1 averaging = 2)
$CD = $4205 (hi threshold)
$CD = $0200 (lo threshold)
$A7 = $0030 (turn AuxADC1 on)
Note that threshold levels may need adjustment to suit particular hardware implementations.
5.2.7 RSSI Measurement (I/Q Mode only)
In I/Q mode the RSSI is calculated from the signal levels present at the I and Q inputs and the AGC levels
currently in use. Figure 8 shows a typical response.
2014 CML Microsystems Plc
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