AIS Baseband IC with/without RF Synthesiser
CMX7032/CMX7042
7.10 System Clock Synthesisers
Two System Clock outputs, SYSCLK1and SYSCLK2, are available to drive additional circuits, as required.
These are phase locked loop (PLL) clocks that can be programmed via the System Clock registers with
suitable values chosen by the user. The System Clock PLL Configuration registers ($AB and $AD) control
the values of the VCO Output divider and Main Divide registers, while the System Clock Ref. Configuration
registers ($AC and $AE) control the values of the Reference Divider and signal routing configurations. The
PLLs are designed for a reference frequency of 96kHz.
The System Clock output divider stages are designed so that they have a 1:1 Mark-to-Space ratio when an
even divide number is selected.
to RF Synthesiser
Ref CLK selection
SysCLK1 VCO
24.576-
98.304MHz
LPF
VCO
(49.152MHztyp)
Ref CLK div
/1 to 512
$AC b0-8
PLL div
/1 to 1024
$AB b0-9
PD
SysCLK1
Ref
SysCLK1
Div
48 - 192kHz
(96kHztyp)
VCO op div
/1 to 64
$AB b10-15
SysCLK1
Pre-CLK
SysCLK1
Output
$AC b11-15
384kHz-50MHz
SysCLK2 VCO
24.576-
LPF
VCO
98.304MHz
(49.152MHztyp)
Ref CLK div
/1 to 512
$AE b0-8
PLL div
/1 to 1024
$AD b0-9
PD
SysCLK2
Ref
SysCLK2
Div
48 - 192kHz
(96kHztyp)
VCO op div
/1 to 64
$AD b10-15
SysCLK2
Pre-CLK
SysCLK2
Output
$AE b11-15
384kHz-50MHz
9.6MHzXtal or
19.2MHZ Clock
MainCLK
OSC
Figure 18 System Clock Generation
The CMX7032/CMX7042 includes a 2-pin crystal oscillator circuit. This can either be configured as a
9.6MHz xtal oscillator, or the XTAL/CLK input can be driven by an externally generated 19.2MHz clock.
Note that, at power-on, the CMX7032 will provide the XTAL/CLK input to both System Clock output pins,
whereas the CMX7042 will inhibit both outputs until they are enabled by a host command over the C-BUS.
2012 CML Microsystems Plc
47
D/7032/42_FI1.2/13
CMLMICRO [ CML MICROCIRCUITS ]
