AIS Baseband IC with/without RF Synthesiser
CMX7032/CMX7042
Figure 17 Single RF PLL Block Diagram
The two RF phase locked loops (PLLs) are programmable to any frequency in the range 100MHz to
600MHz. Figure 17 is a block diagram of one PLL. The RF synthesiser clock is the same 9.6MHz or
19.2MHz clock as is used by the baseband circuitry. The RF synthesiser clock is common to both PLLs.
The charge pump supply (CPV ) is also common to both PLLs. The RF input pins (RFnN and RFnP),
DD
CPnOUT, ISETn and RFV
pins are PLL specific and designated as either RF1P, RF1N, CP1OUT,
SS
ISET1, RFV
or RF2P, RF2N, CP2OUT, ISET2, RFV
on the Signal List in section 3. The N and R
SS
SS
values for Tx and Rx modes are PLL specific and can be set from the host µC via the C-BUS. Various PLL
specific status signals are also accessible via C-BUS. The divide by N counter is 20 bits; the R counter is
13 bits.
The PLL step size (comparison frequency) is programmable: to minimise the effects of phase noise this
should be kept as high as possible. This can be set as low as 2.5kHz (for a reference input of 20MHz or
less), or up to 200kHz – limited only by the performance of the phase comparator.
The frequency for each PLL is set by using two registers: an ‘R’ register that sets the division value of the
input reference frequency to the comparison frequency (step size), and an ‘N’ register that sets the division
of the required synthesised frequency from the external VCO to the comparison frequency. This yields the
required synthesised frequency (Fs), such that:
Fs = (N / R) x FREF
where FREF is the selected reference frequency
Since the set-up for the PLLs takes 4 x “RF PLL Data register” writes it follows that, while updating the PLL
settings, the registers may contain unwanted or intermediate values of bits. These will persist until the last
register is written. It is intended that users should change the content of the “RF PLL Data register” on a
PLL that is disabled, powersaved or selected to work from the alternate register set (“Tx” and “Rx” are
alternate register sets). There are no interlocks to enforce this intention. The names “Tx” and “Rx” are
arbitrary and may be assigned to other functions as required. They are independent sets of registers, one
of which is selected to command each PLL by changing the settings in the RF PLL Control register, $B3.
Other parameters for the PLLs are the charge pump setting (high or low). Two levels of charge pump gain
are available to the user, to facilitate the possibility of locking at different rates under program control. A
current setting resistor (R31) is connected between the ISETn pin (one for each PLL system) and the
respective RFV . This resistor will have an internally generated band gap voltage expressed across it
SS
and may have a value of 0 to 30k, which (in conjunction with the on-chip series resistor of 9.6k) will
give charge pump current settings over a range of 2.5mA down to 230µA (including the control bit variation
of 4 to 1). The value of the current setting resistor (R31) is determined in accordance with the following
formulae:
2012 CML Microsystems Plc
45
D/7032/42_FI1.2/13
CMLMICRO [ CML MICROCIRCUITS ]
