AIS Baseband IC with/without RF Synthesiser
CMX7032/CMX7042
gain bit set to 1:
gain bit cleared to 0:
where Icp is the charge pump current (in mA).
R31 (in ) = (24/Icp) – 9600
R31 (in ) = (6/Icp) – 9600
Note that the charge pump current should always be set to at least 230µA.
The 'gain bit' refers to either bit 3 or bit 11 in the RF PLL Control register, $B3.
For optimum performance, a common master clock should be used for the RF synthesisers (RFCLK) and
the baseband sections (Main and Auxiliary System Clocks). Using unsynchronised clocks can result in
spurious products being generated in the synthesiser output and in some cases difficulty may be
experienced with obtaining lock in the RF synthesisers. Typical external components for a complete RF
synthesiser are shown in Figure 16.
Lock Status
The lock status can be observed by reading the RF PLL Status register, $B4, and the individual lock status
bits can (subject to masking) provide a C-BUS interrupt.
The lock detector can use a tolerance of one cycle or four cycles of the reference clock (not the divided
version that is used as a comparison frequency) in order to judge phase lock. An internal shift register
holds the last three lock status measurements and the lock status bits are flagged according to a majority
vote of these previous three states. Hence, one occasional lock error will not flag a lock fail. At least two
successive phase lock events are required for the lock status to be true. Note that the lock status bits
confirm phase lock to the measured tolerance and not frequency lock. The synthesiser may take more
time to confirm phase lock with the lock status bits than the time to switch from channel to channel. The
purpose of a 4-cycle tolerance is for the case where a high frequency reference oscillator would not forgive
a small phase error.
RF Inputs
The RF inputs are differential and self-biased (when not powersaved). They are intended to be capacitively
coupled to the RF signal. The signal should be in the range 0dBm to –20dBm (not necessarily balanced).
To ensure an accurate input signal the RF should be terminated with 50Ω as close to the chip as possible
and with the “P” and “N“ inputs capacitively coupled to the input and ground, keeping these connections as
short as possible. The RF input impedance is almost purely capacitive and is dominated by package and
printed circuit board parasitics.
Guidelines for using the RF Synthesisers
RF input slew rate (dv/dt) should be 14 V/µs minimum.
The RF Synthesiser 2.5V digital supply (RFVDD) can be powered from the VDEC output pin.
RF clock sources and other, different clock sources must not share common IC components,
as this may introduce coupling into the RF. Unused ac-coupled clock buffer circuits should
be tied to a dc supply, to prevent them oscillating. By default the RF clock source is routed to
the XTAL/CLK input internally.
It is recommended that the RF Synthesisers are operated with maximum gain Iset (ie. ISETn
tied to RFV ).
SS
The loop components should be optimised for each VCO.
2012 CML Microsystems Plc
46
D/7032/42_FI1.2/13
CMLMICRO [ CML MICROCIRCUITS ]
