AIS Baseband IC with/without RF Synthesiser
CMX7032/CMX7042
4. apply the RSSI_gain value
5. accumulate values over the defined period
6. output values to C-BUS registers
Note that the RSSI measurements on each RF channel run consecutively and that the C-BUS registers
are updated at the end of the RSSI_2 measurement window.
7.4.10 RSSI Calibration
The RSSI signal should be approximately logarithmically scaled (i.e. a nearly linear relationship between
voltage and signal strength in dBs). In order to reduce the impact of noise, the CMX7032/CMX7042
averages over several samples, but to give a meaningful average, the samples must first be anti-logged.
In order to correct any non-linearities in the RSSI response, and to set an offset for the anti-logging, the
host must supply calibration data.
The calibration data is a 128-entry table. The entries correspond to equally-spaced voltages from 0V to
3.3V (nominal – see 8.1.3) applied to the RSSI inputs. To set up the table the host uses the RSSI_Lookup
config task. See section 7.8 for details. The default values are shown in User Manual section 9.19.2.3.
7.4.11 ADCs
The first ADC is dedicated to RSSI measurements at times specified by the host µC, see Section 7.4.8
and User Manual 9.19.2.4. The second ADC is available for user functions. The ADC runs continuously,
the input selected by the ADC Input Select bits in the C-BUS Mode register, $C1 and the results of the
conversion are presented in ADC Data C-BUS register $C9. This register also includes a bit field to
indicate which input was selected when this conversion was executed. The ADC input can be routed to
either of the RXnN signals, the SpareN input, the RSSI inputs or the ADC inputs under host control. In
normal operation it is expected to be routed to one of the ADC Inputs.
7.4.12 DACs
The four DACs can be updated in any combination using the DAC_Write data task. See User Manual 9.19
In addition, DAC1 can be configured as a RAMDAC to output a series of values as part of the transmit
timing sequence. The values and the rate at which they change are set-up using a Config mode task.
7.4.13 Interrupt Operation
The CMX7032/CMX7042 will issue an interrupt on the IRQN line when the IRQ bit (bit 15) of the Status
register and the IRQ Mask bit (bit 15) are both set to 1. User Manual section 9.21 describes the situations
which cause the IRQ bit to change from a 0 to a 1. The IRQN pin is an open collector output that requires
an external pull-up resistor.
7.4.14 Deep Sleep Mode
“Deep Sleep” mode (entered through Configuration mode) puts the device into static state where all signal
processing and clocks are stopped and only the C-BUS remains active. In this mode, the I drops to the
DD
lowest level, as specified in section 8.1.3, and is thus suitable for use on Aids to Navigation, or other
implementations where it is feasible for the host µC to switch off the CMX7032/CMX7042 at known times.
See User Manual section 9.19.2.11.
7.5 Operation of Tasks
This section describes modem and data tasks. Understanding their operation requires knowledge of the
internal buffering of the CMX7032.
Tx and Rx data is double buffered. Each Tx or Rx channel has a Data Buffer. The host µC accesses the
C-BUS registers and the modulator/demodulator directly accesses the Data Buffers. Tasks transfer data
between the buffers and the C-BUS registers.
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CMLMICRO [ CML MICROCIRCUITS ]
