AIS Baseband IC with/without RF Synthesiser
CMX7032/CMX7042
7.5.3 Registers and Buffers for Tx/Rx Tasks
Command register: contains Data and Modem task fields as described above.
Status register: contains bits that indicate when tasks are complete, which can interrupt the host:
o
o
o
o
o
o
o
o
o
Command Reg Free
TBFREE
R1BRDY
R2BRDY
TxDONE
Rx1BOVF
Rx2BOVF
Config Task Complete
Data Task Complete
Interrupt Mask: Host write register to specify which status bit can cause an interrupt.
Write Data registers 0-3: Contain data written from host µC to transmit via the Tx Modulator.
Read Data registers 0-3: Contain data received from Rx Demod for host µC to read.
Tx Data Buffer: The Tx Data is double buffered, which allows the host µC to write to the Tx Data
Buffer while the modulator is simultaneously transmitting data it reads from the Tx Modem Buffer.
Each buffer is capable of holding one full (5-slot) AIS message.
Rx1/2 Data Buffer: The demodulator writes data directly into these internal buffers. There are two
buffers per channel which are used alternately every time a new burst is detected. This allows the
host µC to read from one buffer while reception continues to fill the other. Each buffer is capable
of holding a full (5-slot) AIS message.
7.5.4 Write Data Registers
An array of four, 16 bit, C-BUS write registers form the Write Data C-BUS registers.
The device reads and acts upon the content of these data write registers as instructed by the Data Task
bits of the Command register while in transmit mode. Generally, they may be written at any time by the
host µC with no effect on internal device operation. When a “Data task” is issued the Data registers will be
read by the device and so should not be modified by the host µC until the Data Task complete bit is set in
the Status register.
Data tasks access the registers as a number of words (1 to 4) or as a number of bits (1 to 16 in $A7),
however if a bit-format Data Task is used it must be the final data task issued in a multi-data transfer from
the host. The next data task issued should be a DataWordResetN_Tx or DataBitResetN_Tx to re-initialise
the internal data buffer pointers (a bit-format task is usually used as the last transfer of a data block that is
not a complete number of words in length).
Word-format:
Bit:
Register $A7
Bit:
Register $A8
Bit:
Register $B6
Bit:
Register $B7
15
15
15
15
14
14
14
14
13
13
13
13
12
12
12
12
11
Data write from host µC to device word 1(MSB sent first)
11 10
Data write from host µC to device word 2(MSB sent first)
11 10
Data write from host µC to device word 3(MSB sent first)
11 10
Data write from host µC to device word 4(MSB sent first)
10
9
8
7
6
5
4
3
3
3
3
2
2
2
2
1
1
1
1
0
0
0
0
9
8
7
6
5
4
9
8
7
6
5
4
9
8
7
6
5
4
Bit-format:
Bit:
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Register $A7
Data write from host µC to device bits 0-15, (bit 15 transmitted first)
2012 CML Microsystems Plc
31
D/7032/42_FI1.2/13
CMLMICRO [ CML MICROCIRCUITS ]
