AX.25 Modem
CMX7031/CMX7041
3
Signal List
CMX7031 CMX7041
Signal
Name
Type
64-pin
Q1/L9
48-pin
Q3/L4
Description
C-BUS: A 'wire-ORable' output for connection to the Interrupt
Request input of the host. Pulled down to DVSS when active
and is high impedance when inactive. An external pull-up
resistor (R1) is required.
8
IRQN
OP
1
-
-
-
-
-
RF1N
RF1P
IP
IP
RF Synthesiser #1 Negative input.
RF Synthesiser #1 Positive input.
2
3
4
5
6
RFVSS
CP1OUT
ISET1
PWR The negative supply rail (ground) for the 1st RF synthesiser.
OP
IP
1st Charge Pump output.
1st Charge Pump Current Set input.
The 2.5V positive supply rail for the RF synthesisers. This
-
RFVDD
PWR should be decoupled to RFVSS by a capacitor mounted close
to the device pins.
7
-
-
-
-
-
RF2N
RF2P
IP
IP
RF Synthesiser #2 Negative input.
RF Synthesiser #2 Positive input.
8
9
RFVSS
CP2OUT
ISET2
PWR The negative supply rail (ground) for the 2nd RF synthesiser.
10
11
12
OP
IP
2nd Charge Pump output.
2nd Charge Pump Current Set input.
The 3.3V positive supply rail for the RF charge pumps. This
-
CPVDD
PWR should be decoupled to RFVSS by a capacitor mounted close
to the device pins.
13
1
-
-
-
-
RFCLK
GPIOA
GPIOB
-
IP
14
15
16
17
RF Clock Input (common to both synthesisers) .
IP/OP General Purpose I/O pin (CMX7031 only).
IP/OP General Purpose I/O pin (CMX7031 only).
NC
PWR
OP
Reserved – do not connect this pin.
Internally generated 2.5V digital supply voltage. Must be
decoupled to DVSS by capacitors mounted close to the
device pins. No other connections allowed, except for
9
VDEC
18
optional connection to RFVDD
.
10
11
12
13
14
-
RXENA
GPIOA
GPIOB
SYSCLK1
DVSS
Rx Enable – active low when in Rx mode ($C1:b0 = 1).
19
-
IP/OP General Purpose I/O pin (CMX7041 only).
IP/OP General Purpose I/O pin (CMX7041 only).
-
OP
Synthesised Digital System Clock Output 1.
20
21
22
23
24
25
PWR Digital Ground.
-
NC
OP
IP
Reserved – do not connect this pin.
15
16
17
TXENA
DISCN
DISCFB
Tx Enable – active low when in Tx mode ($C1:b1 = 1)
Channel 1 inverting input.
OP
Channel 1 input amplifier feedback.
1
To minimise crosstalk, this signal should be connected to the same clock source as XTAL/CLOCK input.
Page 7 D/7031/7041_FI-4.x/5
2013 CML Microsystems Plc
CMLMICRO [ CML MICROCIRCUITS ]
