AX.25 Modem
CMX7031/CMX7041
3
Signal List
CMX7041
48-pin
Q3/L4
Signal
Name
Type
Description
C-BUS: A 'wire-ORable' output for connection to the Interrupt
Request input of the host. Pulled down to DV
SS
when active
and is high impedance when inactive. An external pull-up
resistor (R1) is required.
RF Synthesiser #1 Negative input.
RF Synthesiser #1 Positive input.
The negative supply rail (ground) for the 1st RF synthesiser.
1st Charge Pump output.
1st Charge Pump Current Set input.
The 2.5V positive supply rail for the RF synthesisers. This
should be decoupled to RFV
SS
by a capacitor mounted close
to the device pins.
RF Synthesiser #2 Negative input.
RF Synthesiser #2 Positive input.
The negative supply rail (ground) for the 2nd RF synthesiser.
2nd Charge Pump output.
2nd Charge Pump Current Set input.
The 3.3V positive supply rail for the RF charge pumps. This
should be decoupled to RFV
SS
by a capacitor mounted close
to the device pins.
RF Clock Input (common to both synthesisers)
1
.
General Purpose I/O pin (CMX7031 only).
General Purpose I/O pin (CMX7031 only).
Reserved – do not connect this pin.
Internally generated 2.5V digital supply voltage. Must be
decoupled to DV
SS
by capacitors mounted close to the
device pins. No other connections allowed, except for
optional connection to RFV
DD
.
Rx Enable – active low when in Rx mode ($C1:b0 = 1).
General Purpose I/O pin (CMX7041 only).
General Purpose I/O pin (CMX7041 only).
Synthesised Digital System Clock Output 1.
Digital Ground.
Reserved – do not connect this pin.
Tx Enable – active low when in Tx mode ($C1:b1 = 1)
Channel 1 inverting input.
Channel 1 input amplifier feedback.
CMX7031
64-pin
Q1/L9
1
8
IRQN
OP
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
RF1N
RF1P
RFVSS
CP1OUT
ISET1
RFVDD
RF2N
RF2P
RFVSS
CP2OUT
ISET2
CPVDD
RFCLK
GPIOA
GPIOB
-
IP
IP
PWR
OP
IP
PWR
IP
IP
PWR
OP
IP
PWR
IP
IP/OP
IP/OP
NC
18
9
VDEC
PWR
19
-
-
20
21
22
23
24
25
10
11
12
13
14
-
15
16
17
RXENA
GPIOA
GPIOB
SYSCLK1
DVSS
-
TXENA
DISCN
DISCFB
OP
IP/OP
IP/OP
OP
PWR
NC
OP
IP
OP
1 To minimise crosstalk, this signal should be connected to the same clock source as XTAL/CLOCK input.
2013 CML Microsystems Plc
Page 7
D/7031/7041_FI-4.x/5
CMLMICRO [ CML MICROCIRCUITS ]
