AX.25 Modem
CMX7031/CMX7041
Averaging can be applied to the ADC readings by selecting the b2-0 in the Program Block P1.2 and P1.3.
This is a rolling average system such that a proportion of the current data value will be added to the last
value. The proportion is determined by the value of the average counter.
Table 6 Averaging Values
% of current sample
value used
100%
% of previous average
P1.2/P1.3:b2-0
used
0%
50%
75%
87.5%
93.75%
96.875%
000
001
010
011
100
101
0
1
2
3
4
5
50%
25%
12.5%
6.25%
3.125%
High thresholds may be independently applied to both ADC channels (the comparison is applied after
averaging, if this is enabled) and an IRQ generated if a rising edge passes the high threshold. This feature
can be used to as a “Carrier Detect” function when the input is connected to a suitable RF level
measurement point in the RF hardware. The thresholds are programmed via the Program Block, P1.0 and
P1.1.
Auxiliary ADC data is read back in the AuxADC Data registers ($A9 and $AA) and includes the threshold
status as well as the actual conversion data (subject to averaging, if enabled).
IRQ
IRQ
High
Threshold
Signal
Figure 15 AuxADC IRQ Operation
See:
o
o
AuxADC1 Data - $A9 16-bit read
AuxADC2 Data - $AA 16-bit read
7.8
Auxiliary DAC/RAMDAC Operation
The four auxiliary DAC channels are programmed via the AuxDAC Control register, $A8. AuxDAC channel
1 may also be programmed to operate as a RAMDAC which will automatically output a pre-programmed
profile at a programmed rate.
The default profile is a raised cosine (see Table 11), but this may be over-written with a user defined
profile by writing to Programming Block P3.11. The RAMDAC operation is only available in Tx mode and,
to avoid glitches in the ramp profile, it is important not to change to IDLE or Rx mode whilst the RAMDAC
is still ramping. The AuxDAC outputs hold the user-programmed level during a powersave operation if left
enabled, otherwise they will become tri-state (high impedance). Note that access to all four AuxDACs is
controlled by the AuxDAC Control register, $A8, and therefore to update all AuxDACs requires four writes
to this register. It is not possible to simultaneously update all four AuxDACs.
2013 CML Microsystems Plc
Page 28
D/7031/7041_FI-4.x/5
CMLMICRO [ CML MICROCIRCUITS ]
