AX.25 Modem
CMX7031/CMX7041
Typical stages of Tx operation are depicted in Figure 10 and occur as follows:
1. The host writes up to four words of data for transmission into the TxData C-BUS registers.
2. The host writes to the TxData Count register, specifying the number of bytes/bits to transfer
This results in the transfer of the data from the TxData registers into the Tx Data Buffer.
3. Steps 1 and 2 can be repeated to load the Tx Data Buffer with a large block of data.
4. The Mode bits are set to Tx, which causes the Tx sequencer to activate and data to be NRZId
(and scrambled in the case of 9600bps mode) and passed to the Tx Modulator and transmitted to
the MOD1 and MOD2 output pins.
5. This will continue until such time that the host notifies the device by setting the “Last Data” bit in
the TxData Count register, at which point the Modulator will cease operation once the last data bit
has been transmitted. At this point the Tx sequencer will de-activate and the TxENA line will return
to its inactive state and assert the TxDone IRQ when the host may turn off any other directly
controlled Tx circuits/processes. The sequencer automatically compensates for data transfer and
internal processing/filtering delays.
6. If the host does not supply sufficient data, a data famine condition will be indicated and the Tx
sequencer will execute as if the “Last Data” flag had been asserted.
Modem Control Register
TxENA
C-BUS
registers
1200bps
Modulator
C
B
C
A
B
7
B
6
Tx Data Buffer
(128 words)
NRZI
9600bps
Modulator
Scrambler
Data Ready
TxDone
Figure 10 Tx Operation
7.6.3 Receiving AFSK/GMSK Data
When enabled and subsequent to the sync sequence being detected, the selected demodulator will NRZI
the data and deliver data bits to the internal Rx buffer. This data is transferred to the C-BUS RxData block
and the RxDataRDY IRQ activated.
2013 CML Microsystems Plc
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