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CMX608 参数 Datasheet PDF下载

CMX608图片预览
型号: CMX608
PDF下载: 下载PDF文件 查看货源
内容描述: [Integrated Input and Output Channel Filters]
分类和应用:
文件页数/大小: 70 页 / 3411 K
品牌: CMLMICRO [ CML MICROCIRCUITS ]
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RALCWI Vocoder  
CMX608/CMX618/CMX638  
$07 (ECC_CODEC_START)  
Starts the CODEC running. The exact effect of this command is CODEC dependant. If any of the  
generic CODEC settings are chosen, this command does not do anything. Please refer to the  
external CODEC support section.  
$08 (ECC_CODEC_PSAVE)  
Places the CODEC in a powersave state. The exact effect of this command is CODEC  
dependant. If any of the generic CODEC settings are chosen, this command does not do  
anything. Please refer to the external CODEC support section.  
$09 (ECC_EEC_LOW)  
Set the output port EEC low, without affecting the REC port. Using this command removes the  
need to hold a shadow register for the port states.  
$0A (ECC_EEC_HIGH)  
Set the output port EEC high, without affecting the REC port. Using this command removes the  
need to hold a shadow register for the port states.  
$0B (ECC_REC_LOW)  
Set the output port REC low, without affecting the EEC port. Using this command removes the  
need to hold a shadow register for the port states.  
$0C (ECC_REC_HIGH)  
Set the output port REC high, without affecting the EEC port. Using this command removes the  
need to hold a shadow register for the port states.  
$0D - $3F Reserved.  
SEL1 / SEL0 = '11' - Reserved  
7
1
6
1
5
4
3
2
1
0
reserved  
IDD register address $0C  
7
6
5
4
3
2
1
0
Delay  
This write-only register controls an initial delay in sending samples to the CODEC after the first  
frame is given to the decoder, once it has been enabled. The value is given in samples (125µs)  
and must be between 1 and 255 inclusive. This register has a default value of 64, which equates  
to a time period of 8ms. Bit 7 is the msb.  
Once the delay has been set, bit 15 (RDY) of the STATUS register ($40) will be set and IRQN will  
go low if C-BUS interrupts are enabled for this bit. After the decoder is enabled, the first frame  
that is given to the device for decoding will start a delay timer primed with the value contained in  
this register. The device will not attempt to send a sample to the CODEC until this timer reaches  
zero. After the timer has expired, it will not be used again until the decoder is disabled, and then  
re-enabled, where receipt of the first frame will again start the timer.  
This delay period is required in order to eliminate the effect of the algorithmic jitter in the decoder  
algorithm. If additional algorithmic jitter is present in frame acquisition and presentation (perhaps  
from a demodulator, or from scheduling effects in the host) then this delay may need to be  
increased to prevent the CODEC from suffering sample starvation during the first few frames.  
Please see section 5.3 for further information.  
2014 CML Microsystems Plc  
41  
D/608_18_38/11  
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