RALCWI Vocoder
CMX608/CMX618/CMX638
CMX618/CMX638 in external CODEC mode, the SYNC output is not available, so another method needs
to be employed, e.g using a modulo 160 counter clocked by the CODEC frame sync.
Timed
It is assumed that the host has an accurate 20ms timer, derived from the master clock of the system,
which may or may not be synchronous with the audio CODEC. Wait for a timer event, instruct the device
to decode, and then supply a packet for decoding. For every subsequent timer event, supply another
packet for decoding. This is essentially the same as the event driven / method 2 above, the difference
being that if the timer is not synchronous with the CODEC then the device's slip management feature will
have to be employed. Further details of slip management are given in section 6.5.
The following diagrams show various aspects of the timed delivery of single-frame raw Vocoder packets
for decoding.
Figure 10 Single Frame Packet Decoding
Figure 10 shows the sequence of events including the initial decoder delay, which compensates for the
decoder's algorithmic jitter.
Figure 11 Single Frame Packet Decoding with Host Jitter
Figure 11 shows the effect of 4ms of host jitter with a default value of 8ms for the initial decoder delay.
After the second batch of samples there is a gap, where the worst case of early delivery followed by late
delivery has caused the CODEC to be starved of samples. To avoid this situation, the IDD has to be
increased.
2014 CML Microsystems Plc
18
D/608_18_38/11
CMLMICRO [ CML MICROCIRCUITS ]
