RALCWI Vocoder
CMX608/CMX618/CMX638
The exact rate at which packets must be presented is dependant on the accuracy of the CODEC's sample
rate. The nominal rate is every 20ms, or a multiple thereof, depending on the number of frames that make
up the packet. For instance, a packet of 3 frames with FEC will be produced every 60ms. The algorithm
used to decode the encoded voice has algorithmic jitter, i.e. it does not take the same amount of time to
decode each frame. Some frames will take longer than others. An initial delay in sending samples to the
CODEC, coupled with an output buffer, will ensure that the CODEC is not starved of samples. It is also
possible for the decoder to indicate that a new packet should be presented for decoding, based upon the
number of samples left in the output buffer.
5.3.1.
Single Frame Packet, without FEC, STD or DTMF
This is the simplest and most basic configuration. The decoder will produce 20ms of audio for each
single-frame raw Vocoder packet.
Once the decode instruction is given, the device will wait for single-frame raw Vocoder packets to arrive
every 20ms. Once the first packet is received, the initial decoder delay timer will be started, the frame will
be decoded into 20ms of audio samples and the resulting samples placed in the output buffer. After the
samples have been placed in this buffer, the device will wait for the initial decoder delay (IDD) timer to
expire before sending the first sample to the CODEC. After this initial delay, further samples are given to
the CODEC at its sample rate. The initial delay is set to be greater than the maximum time it takes to
decode a frame. This ensures that the CODEC will not be starved of samples if the subsequent frame
takes longer to decode than the first frame. The default initial decoder delay is set to 64 samples (8ms),
which is more than sufficient to cover the internal algorithmic jitter. If the host, either through its internal
scheduling or as a result of any algorithmic jitter in any processing that has to occur (e.g. demodulation),
cannot supply the packets at exactly the right time (even though the average interval is correct), this initial
delay should be increased to cover the additional jitter. The IDD ($0C) register has been provided in order
to facilitate the adjustment of this delay.
The CMX608 and CMX618 can be configured to set the STATUS ($40) register bit 8 (VDW Vocoder Data
Wanted) to '1' whenever there are fewer than a certain number of samples left in the output buffer. This is
controlled by the low and high watermarks, which are set by using the VDWHLWM ($1E) register. When
the number of samples left in the output buffer is less than or equal to the low watermark, VDW will be set
to '1' (and a C-BUS interrupt will occur, if enabled). Once indicated, the VDW bit cannot be set again until
the output buffer has had at least 'high watermark' samples in it. This hysteresis prevents constant
indication or interrupts when the number of samples in the buffer is still less than the low watermark.
There are three basic strategies that can be adopted for driving the decoder:
Event driven / Method 1
The host may use the C-BUS interrupt, IRQN, or poll the STATUS register, then supply a Vocoder packet
as soon as the VDW bit is set. For this method the low and high watermarks must be set to suitable
values. As an example, given that the decoder algorithm will take no more than 8ms to process a frame,
and that the host can respond to the STATUS register having its VDW bit set within 1 ms, the low
watermark should be set for a time period of 9ms, where 9ms at 8000 samples per second equates to a
period of 72 samples. The high watermark should be set to a few samples less than 160. This value is
not critical, providing it is greater than the low watermark.
The host should send the first packet to the device, after which it should wait, either by polling or by
making use of the C-BUS interrupt, for the VDW bit to be set to '1'. Once this bit is set, the next packet
should be sent to the device. The process should be repeated for as long as there are packets to decode.
This method is an ideal choice for a voice record/playback system.
Event driven / Method 2
The device can be set up to produce a short pulse every 20ms on the SYNC pin (pin 25). This pulse can
be used to signal an interrupt to the controlling host, which can then cause a packet of data to be sent to
the Vocoder. The 20ms period is directly related to the sample rate of the internal CODEC. This will only
work for a CMX618/CMX638 set up for using its internal CODEC. For the CMX608, or the
2014 CML Microsystems Plc
17
D/608_18_38/11
CMLMICRO [ CML MICROCIRCUITS ]
