CPC7592
2.3.5 Break-Before-Make Operation - All Versions
The second break-before-make method for the
CPC7592xA/B is also the only method available for
the CPC7592xC. As shown in “CPC7592xA and
CPC7592xB Truth Table” on page 10 and
prevents any other switches from closing.
2. Keep T low for at least one-half the duration of
SD
the ringing cycle period to allow sufficient time for
a zero crossing current event to occur and for the
circuit to enter the break-before-make state.
“CPC7592xC Truth Table” on page 10, the
bi-directional T interface disables all of the
3. During the T low period, set the IN
and
SD
SD
RINGING
CPC7592 switches when pulled to a logic low.
Although logically disabled, an active (closed) ringing
switch (SW4) will remain closed until the next zero
crossing current event.
IN
inputs to the talk state (0, 0).
TEST
4. Release T , allowing the internal pull-up to
SD
activate the break switches.
When using T as an input, the two recommended
SD
As shown in the table “Break-Before-Make Ringing to
Talk Transition Logic Sequence for all Versions” on
page 14, this operation is similar to the one shown in
“Break-Before-Make Operation - All Versions” on
page 14, except in the method used to select the all off
states are “0” which overrides the logic input pins and
forces an all off state and “Z” which allows normal
switch control via the logic input pins. This requires the
use of an open-collector or open-drain type buffer.
state, and in when the IN
are reconfigured for the talk state.
and IN
inputs
RINGING
TEST
Forcing T to a logic high disables the thermal
SD
shutdown circuit and is therefore not recommended as
this could lead to device damage or destruction in the
presence of excessive tip or ring potentials.
1. Pull T to a logic low to end the ringing state.
SD
This opens the ringing return switch (SW3) and
Break-Before-Make Ringing to Talk Transition Logic Sequence for all Versions
Ringing
Return
Switches Switch
(SW3)
Ringing
Switch
(SW4)
Break
Test
Switches
INRINGING
INTEST
TSD
State
LATCH
Timing
Ringing
All-Off
1
1
0
0
0
Z
-
Off
On
On
On
Off
Off
Hold this state for at least one-half of the
ringing cycle. SW4 waiting for zero current to
turn off.
Off
Off
X
0
0
Z
Break-
Before-
Make
0
0
0
0
SW4 has opened
Off
On
Off
Off
Off
Off
Off
Off
Talk
Close Break Switches
2.4 Data Latch
The CPC7592 has an integrated transparent data
latch. The latch enable operation is controlled by TTL
logic input levels at the LATCH pin. Data input to the
Whenever the LATCH enable control pin is at logic 1,
the data latch is active and data is locked. Subsequent
changes to the input controls IN
and IN
RINGING
TEST
latch is via the input pins IN
and IN
while
will not result in a change to the control logic or affect
the existing switch state.
RINGING
TEST
the output of the data latch are internal nodes used for
state control. When the LATCH enable control pin is at
a logic 0 the data latch is transparent and the input
control signals flow directly through the data latch to
the state control circuitry. A change in input will be
reflected by a change in the switch state.
The switches will remain in the state they were in
when the LATCH changes from logic 0 to logic 1 and
will not respond to changes in input as long as the
LATCH is at logic 1. However, neither the T input
SD
nor the T output control functions are affected by
SD
the latch function. Since internal thermal shutdown
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