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CPC7583MBTR 参数 Datasheet PDF下载

CPC7583MBTR图片预览
型号: CPC7583MBTR
PDF下载: 下载PDF文件 查看货源
内容描述: 线卡接入交换机 [Line Card Access Switch]
分类和应用: 电信集成电路光电二极管
文件页数/大小: 21 页 / 619 K
品牌: CLARE [ CLARE ]
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CPC7583  
20 Hz ringing hold this input state for 25 ms. During  
this hold period, toggle the inputs from the ringing  
state to the talk state. After the 25 ms, release T to  
SD  
return switch control to the input pins IN  
,
TESTout  
IN  
, IN  
and the latch control pin.  
RINGING  
TESTin  
2.2.1 Make-Before-Break Operation (Ringing to Talk Transition)  
Break  
Ring  
Switches Return Access  
Ring All Other  
IN  
IN  
IN  
T
SD  
State  
Latch  
Timing  
Test  
1 and 2 Switch 3 Switch 4 Switches  
RINGING  
TESTIN  
TESTOUT  
Ringing  
1
0
0
Floating  
-
Off  
On  
On  
Off  
On  
On  
Off  
SW4 waiting for next  
zero-current crossing to turn  
off. Maximum time is one-half  
of ringing. In this transition  
Make-  
before-  
break  
0
0
0
Floating state, current that is limited to  
the dc break switch current  
limit value will be sourced  
from the ring node of the  
SLIC.  
Off  
0
Zero-cross current has  
Talk  
0
0
0
Floating  
occurred  
On  
Off  
Off  
Off  
2.2.2 Break-Before-Make Operation (Ringing to Talk Transition)  
Break  
Ring  
Ring All Other  
Test  
1 and 2 Switch 3 Switch 4 Switches  
IN  
IN  
IN  
T
SD  
State  
Latch  
Timing  
Switches Return Access  
RINGING  
TESTIN  
TESTOUT  
Ringing  
All off  
1
1
0
0
0
1
Floating  
-
Off  
On  
On  
Off  
Hold this state for one-half of  
Floating ringing cycle. SW4 waiting for  
zero current to turn off.  
Off  
Off  
On  
Off  
0
Zero current has occurred.  
Floating  
All off  
Talk  
1
0
0
0
1
0
Off  
On  
Off  
Off  
Off  
Off  
Off  
Off  
SW4 has opened  
Floating  
Close break switches  
2.3 Alternate Break-Before-Make Operation  
Note that break-before-make operation can also be  
2.4 Data Latch  
The CPC7583 has an integrated data latch. The latch  
achieved using T as an input. In lines 2 and 3 of the  
operation is controlled by logic-level input at the  
SD  
LATCH pin. The data input of the latch are the input  
pins, while the output of the data latch is an internal  
node used for state control. When the LATCH control  
pin is at logic 0, the data latch is transparent and data  
control signals flow directly through to state control. A  
change in input will be reflected by a change in switch  
state. When the LATCH control pin is at logic 1, the  
data latch is active and a change in input control will  
not affect switch state. The switches will remain in the  
position they were in when the LATCH changed from  
table “Break-Before-Make Operation (Ringing to Talk  
Transition)” on page 15, instead of using the logic input  
pins to force the all-off state, force T to ground. This  
SD  
overrides the logic inputs and also forces the all off  
state. Hold this state for one-half of the ringing cycle.  
During this T forced all-off state, change the inputs  
SD  
from the power ringing state (IN  
= 1, IN  
= 0,  
RING  
TESTIN  
IN  
IN  
= 0) to the talk state (IN  
= 0,  
TESTOUT  
RING  
= 0, IN  
= 0). After the hold period,  
TESTIN  
TESTOUT  
release T to return switch control to the input pins  
SD  
which will set the talk state.  
R06  
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