EP9315
Enhanced Universal Platform SOC Processor
Table T illustrates the pin signal multiplexing and configuration options.
Table T. Pin Multiplex Usage Information
Physical
Pin Name
Description
Multiplex signal name
COL[7:0]
ROW[7:0]
EGPIO[0]
EGPIO[1]
EGPIO[2]
EGPIO[3]
EGPIO[4]
EGPIO[5]
EGPIO[6]
EGPIO[7]
EGPIO[8]
EGPIO[9]
EGPIO[10]
EGPIO[11]
EGPIO[12]
EGPIO[13]
EGPIO[14]
EGPIO[15]
ABITCLK
ASYNC
GPIO
GPIO Port D[7:0]
GPIO Port C[7:0]
RI
GPIO
Ring Indicator Input
1Hz clock monitor
IDE DMA request
CLK1HZ
DMARQ
Transmit Enable output / HDLC clocks TENn / HDLCCLK1 / HDLCCLK3
I2S Transmit Data 1
I2S Receive Data 1
I2S Transmit Data 2
DMA Request 0
DMA Acknowledge 0
DMA EOT 0
DMA Request 1
DMA Acknowledge 1
DMA EOT 1
I2S Receive Data 2
PWM 1 output
IDE Device active / present
I2S Serial clock
I2S Frame Clock
I2S Transmit Data 0
I2S Receive Data 0
I2S Master clock
I2S Serial clock
I2S Frame Clock
I2S Transmit Data 0
I2S Receive Data 0
GPIO
SDO1
SDI1
SDO2
DREQ0
DACK0
DEOT0
DREQ1
DACK1
DEOT1
SDI2
PWMOUT1
DASP
SCLK
LRCK
ASDO
SDO0
ASDI
SDI0
ARSTn
MCLK
SCLK1
SCLK
SFRM1
LRCK
SSPTX1
SSPRX1
IDEDA[2:0]
IDECS0n
IDECS1n
DIORn
SDO0
SDI0
GPIO Port E[7:5]
GPIO Port E[4]
GPIO Port E[3]
GPIO Port E[2]
GPIO Port E[1]
GPIO Port E[0]
GPIO Port H[7:0]
GPIO Port G[7:4]
GPIO Port G[3:2]
GPIO Port G[1]
GPIO Port G[0]
VS2
GPIO
GPIO
GPIO
GRLED
LED
RDLED
LED
DD[7:0]
GPIO
DD[15:12]
SLA[1:0]
EEDAT
GPIO
GPIO
GPIO
EECLK
GPIO
FGPIO[7]
FGPIO[6]
FGPIO[5]
FGPIO[4]
FGPIO[3]
FGPIO[2]
FGPIO[1]
FGPIO[0]
GPIO
GPIO
READY
GPIO
VS1
GPIO
MCBVD2
MCBVD1
MCD2
GPIO
GPIO
GPIO
MCD1
GPIO
WP
62
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