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EP9315-IBZ 参数 Datasheet PDF下载

EP9315-IBZ图片预览
型号: EP9315-IBZ
PDF下载: 下载PDF文件 查看货源
内容描述: 增强型通用平台的系统级芯片处理器 [Enhanced Universal Platform System-on-Chip Processor]
分类和应用: 微控制器和处理器外围集成电路微处理器时钟
文件页数/大小: 64 页 / 1036 K
品牌: CIRRUS [ CIRRUS LOGIC ]
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EP9315  
Enhanced Universal Platform SOC Processor  
ADC  
Parameter  
Comment  
Value  
Units  
No missing codes  
Range of 0 to 3.3 V  
Resolution  
50K counts (approximate)  
Integral non-linearity  
Offset error  
0.01%  
±15  
mV  
Full scale error  
0.2%  
ADIV = 0  
ADIV = 1  
3750  
925  
Samples per second  
Samples per second  
Maximum sample rate  
ADIV = 0  
ADIV = 1  
500  
2
µs  
ms  
Channel switch settling time  
Noise (RMS) - typical  
120  
µV  
Note:  
ADIV refers to bit 16 in the KeyTchClkDiv register.  
ADIV = 0 means the input clock to the ADC module is equal to the external 14.7456 MHz clock divided by 4.  
ADIV = 1 means the input clock to the ADC module is equal to the external 14.7456 MHz clock divided by 16.  
61A8  
0000  
FFFF  
9E58  
0
Vref/2  
Vref  
A/D Converter Transfer Function  
(approximately ±25,000 counts)  
Figure 38. ADC Transfer Function  
Using the ADC:  
This ADC has a state-machine based conversion engine that automates the conversion process. The initiator for a  
conversion is the read access of the TSXYResult register by the CPU. The data returned from reading this register  
contains the result as well as the status bit indicating the state of the ADC. However, this peripheral requires a delay  
between each successful conversion and the issue of the next conversion command, or else the returned value of  
successive samples may not reflect the analog input. Since the state of the ADC state machine is returned through the  
same channel used to initiate the conversion process, there must be a delay inserted after every complete conversion.  
Note that reading TSXYResult during a conversion will not affect the result of the ongoing process.  
The following is a recommended procedure for safely polling the ADC from software:  
1. Read the TSXYResult register into a local variable to initiate a conversion.  
2. If the value of bit 31 of the local variable is '0' then repeat step 1.  
3. Delay long enough to meet the maximum sample rate as shown above.  
4. Mask the local variable with 0xFFFF to remove extraneous data.  
5. If signed mode is used, do a sign extend of the lower halfword.  
6. Return the sampled value.  
DS638PP4  
©Copyright 2005 Cirrus Logic (All Rights Reserved)  
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