EP9315
Enhanced Universal Platform SOC Processor
AC’97
Parameter
Symbol
tclk_per
tclk_high
tclk_low
tclkrf
Min
Typ
Max
Unit
ABITCLK input cycle time
ABITCLK input high time
ABITCLK input low time
-
81.4
-
45
45
6
ns
ns
ns
ns
ns
ns
ns
ns
ns
36
36
2
-
-
-
-
-
-
-
-
ABITCLK input rise/fall time
ASDI setup to ABITCLK falling
ASDI hold after ABITCLK falling
ASDI input rise/fall time
ts
10
10
2
-
th
-
trfin
6
ABITCLK rising to ASDO / ASYNC valid, CL = 55 pF
ASYNC / ASDO rise/fall time, CL = 55 pF
tco
2
15
6
trfout
2
tclk_high tclk_low
tclk_per
ABITCLK
tclkrf
tclkrf
th
trfin
ts
ASDI
ASDO
trfout
tco
tco
tco
ASYNC
trfout
trfout
Figure 36. AC ‘97 Configuration Timing Measurement
DS638PP4
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