EP9315
Enhanced Universal Platform SOC Processor
Audio Interface
The following table contains the values for the timings of each of the SPI modes.
Parameter
Symbol
tclk_per
tclk_high
tclk_low
tclkrf
Min
Typ
Max
Unit
SCLK cycle time
SCLK high time
SCLK low time
-
-
tspix_clk
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
(tspix_clk) / 2
-
(tspix_clk) / 2
-
SCLK rise/fall time
1
-
-
-
-
-
-
8
3
-
tDMd
Data from master valid delay time
Data from master setup time
Data from master hold time
Data from slave setup time
Data from slave hold time
-
tDMs
20
40
20
40
tDMh
-
tDSs
-
tDSh
-
Note: The tspix_clk is programmable by the user.
DS638PP4
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