EP9312
Universal Platform SOC Processor
t2CYCWR
tCYCWR
tCYCWR
t2CYCWR
HSTROBE
(host)
tDVH
tDVS
tDVH
tDVS
tDVH
DD (15:0)
(host)
HSTROBE
(device)
tDH
tDS
tDH
tDS
tDH
DD (15:0)
(device)
Note: DD (15:0) and HSTROBE signals are shown at both the device and the host to emphasize that cable settling time as well as
cable propagation delay shall not allow the data signals to be considered stable at the device until some time after they are
driven by the host.
Figure 25. Sustained Ultra DMA data-out Burst
DMARQ
(device)
tRP
DMACKn
(host)
STOP
(host)
tSR
DDMARDYn
(device)
tRFS
HSTROBE
(host)
DD (15:0)
(host)
Note: 1. The device may negate DMARQ to request termination of the Ultra DMA burst no sooner than tRP after DDMARDYn is
negated.
2. If the tSR timing is not satisfied, the device may receive zero, one, or two more data words from the host.
Figure 26. Device Pausing an Ultra DMA data-out Burst
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DS515PP7
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