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CS8900A-IQZ 参数 Datasheet PDF下载

CS8900A-IQZ图片预览
型号: CS8900A-IQZ
PDF下载: 下载PDF文件 查看货源
内容描述: 水晶局域网? ISA以太网控制器 [Crystal LAN ⑩ ISA Ethernet Controller]
分类和应用: 微控制器和处理器串行IO控制器通信控制器外围集成电路PC局域网以太网时钟
文件页数/大小: 138 页 / 2374 K
品牌: CIRRUS [ CIRRUS LOGIC ]
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CS8900A  
Crystal LAN™ Ethernet Controller  
tecting the incoming frame's End-of-Frame  
(EOF) sequence.  
Receive Fram e  
Like all Event bits, RxDest and Rx128 are set  
by the CS8900A whenever the appropriate  
event occurs. Unlike other Event bits, RxDest  
and Rx128 may be cleared by the CS8900A  
without host intervention. All other event bits  
are cleared only by the host reading the appro-  
priate event register, either directly or through  
the Interrupt Status Queue (ISQ). (RxDest and  
Rx128 can also be cleared by the host reading  
the BufEvent register, either directly or through  
the Interrupt Status Queue). Figure 22 pro-  
videsadiagramoftheEarlyInterruptprocess.  
Destination  
Address Filter  
Check:  
- PromiscuousA?  
- IAHashA?  
- M ulticastA?  
- IndividualA?  
- BroadcastA?  
Pass  
DA Filter?  
No  
Discard Fram e  
Ye s  
G enerate Early  
Interrupts if Enabled  
(see next figure)  
5.2.3.3 Acceptance Filtering  
The third step of pre-processing is to deter-  
mine whether or not to accept the frame by  
comparing the frame with the criteria pro-  
grammed into the RxCTL register (Register 5).  
If the receive frame passes the Acceptance fil-  
ter, the frame is buffered, either on chip or in  
host memory via DMA. If the frame fails the  
Acceptance filter, it is discarded. The results of  
the Acceptance filter are reported in the Rx-  
Event register (Register 4).  
Acceptance Filter  
Check:  
- RxOKA?  
- ExtradataA?  
- RuntA?  
- CRCerrorA?  
Pa ss  
Accept.  
Filter?  
Ye s  
No  
Status of receive  
fram e reported in  
R xEvent register,  
fram e discarded.  
Status of receive  
fram e reported in  
R xEvent register,  
fram e accepted  
into on-chip R AM  
5.2.3.4 Normal Interrupt Generation  
The final step of pre-processing is to generate  
any enabled interrupts that are triggered by  
the incoming frame. Interrupt generation oc-  
curs when the entire frame has been buffered  
(up to the first 1518 bytes). For more informa-  
tion about interrupt generation, see  
Section 5.1 on page 78.  
G enerate Interrupts  
Check:  
- RxO KiE?  
- ExtradataiE?  
- CRCerroriE?  
- RuntiE?  
5.2.4 Held vs. DMAed Receive Frames  
All accepted frames are either held in on-chip  
RAM until processed by the host, or stored in  
host memory via DMA. A receive frame that is  
held in on-chip RAM is referred to as a held re-  
ceive frame. A frame that is stored in host  
memory via DMA is a DMAed receive frame.  
- RxDM AiE?  
Pre-Processing  
Complete  
Figure 21. Receive Frame Pre-Processing  
CIRRUS LOGIC PRODUCT DATASHEET  
DS271F4  
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