CS8900A
Crystal LAN™ ISA Ethernet Controller
The input pins not included in this test are:
6.1.3 Continuity Cycle
The combination of a complete Output Cycle, a
complete Input Cycle, and an additional AEN cycle
is called a Continuity Cycle. Each Continuity Cycle
lasts for 85 AEN clock cycles. The first Continuity
Cycle can be followed by additional Continuity
Cycles by keeping TEST low and continuing to cy-
cle AEN. When TEST is driven high, the CS8900A
exits Boundary Scan mode and AEN is again used
as the ISA-bus Address Enable.
Pin Name
AEN
TEST
Dl+
Pin #
63
Pin Name
Cl-
Pin #
82
76
RXD+
RXD-
91
79
92
Dl-
80
XTAL1
97
Cl+
81
Table 41.
After the Input Cycle is complete, one more cycle
of AEN returns all digital output pins and bi-direc-
tional pins to a high-impedance state.
Figure 32 shows a complete Boundary Scan Conti-
nuity Cycle.
Figure 33 shows Boundary Scan timing.
CIRRUS LOGIC PRODUCT DATA SHEET
108
DS271PP3
CIRRUS [ CIRRUS LOGIC ]
