CS8900A
Crystal LAN™ ISA Ethernet Controller
6.1 Boundary Scan
The following is a list of output pins and bi-direc-
tional pins that are tested during the Output Cycle:
Boundary Scan test mode provides an easy and ef-
ficient board-level test for verifying that the
CS8900A has been installed properly. Boundary
Scan will check to see if the orientation of the chip
is correct, and if there are any open or short circuits.
Pin Name
ELCS
Pin #
2
Pin Name
INTRQ1
Pin #
31
EECS
3
INTRQ0
32
EESK
4
IOCS16
33
EEDataOut
DMARQ2
DMARQ1
DMARQ0
CSOUT
5
MEMCS16
INTRQ3
34
Boundary Scan is controlled by the TEST pin.
When TEST is high, the CS8900A is configured
for normal operation. When TEST is low, the fol-
lowing occurs:
11
13
15
17
35
IOCHRDY
64
SD0 - SD7 65-68, 71-74
BSTATUS
78
99
SD08-SD15 27-24, 21-18 LINKLED
INTRQ2 30 LANLED
Table 38.
•
the CS8900A enters Boundary Scan test mode
and stays in this mode as long as TEST is low;
100
•
the CS8900A goes through an internal reset and
remains in internal reset as long as TEST is
low;
The output pins not included in this test are:
Pin Name
DO+
Pin #
83
Pin Name
TXD-
Pin #
88
•
•
the AEN pin, normally the ISA bus Address
Enable, is redefined to become the Boundary
Scan shift clock input; and
DO-
84
RES
93
TXD+
87
XTAL2
98
Table 39.
all digital outputs and bi-directional pins are
placed in a high-impedance state (this electri-
cally isolates the CS8900A digital outputs from
the rest of the circuit board).
6.1.2 Input Cycle
During the Input Cycle, the falling edge of AEN
causes the state of each selected pin to be trans-
ferred to EEDataOut (that is, EEDataOut will be
high or low depending on the input level of the se-
lected pin). This cycle begins with SLEEP and ad-
vances clockwise through each of 33 input pins (all
digital input pins except for AEN) and each of the
17 bi-directional pins, one pin at a time.
For Boundary Scan to be enabled, AEN must be
low before TEST is driven low.
A complete Boundary Scan test is made up of two
separate cycles. The first cycle, known as the Out-
put Cycle, tests all digital output pins and all bi-di-
rectional pins. The second cycle, known as the
Input Cycle, tests all digital input pins and all bi-di-
rectional pins.
The following is a list of input pins and bi-direc-
tional pins that are tested during the Input Cycle:
Pin Name
ELCS
Pin #
2
Pin Name
SBHE
Pin #
36
6.1.1 Output Cycle
EEDataIn
CHIPSEL
DMACK2
DMACK1
DMACK0
6
7
12
14
16
SA0 - SA11
REFRESH
SA12 - SA19 50-54, 58-60
37-48
49
During the Output Cycle, the falling edge of AEN
causes each of the 17 digital output pins and each
of the 17 bi-directional pins to be driven low, one
at a time. The cycle begins with LINKLED and ad-
vances in order counterclockwise around the chip
through all 34 pins. This test is referred to as a
"walking 0" test.
IOR
IOW
61
62
SD08-SD15 27-24, 21-18 SD0 - SD7 65-68, 71-74
MEMW
MEMR
28
29
RESET
SLEEP
75
77
Table 40.
CIRRUS LOGIC PRODUCT DATA SHEET
DS271PP3
107
CIRRUS [ CIRRUS LOGIC ]
