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CS8900A-IQ3 参数 Datasheet PDF下载

CS8900A-IQ3图片预览
型号: CS8900A-IQ3
PDF下载: 下载PDF文件 查看货源
内容描述: 水晶局域网? ISA以太网控制器 [Crystal LAN ⑩ ISA Ethernet Controller]
分类和应用: 控制器局域网以太网
文件页数/大小: 128 页 / 1360 K
品牌: CIRRUS [ CIRRUS LOGIC ]
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CS8900A  
Crystal LAN™ ISA Ethernet Controller  
Suffix  
CMD  
CFG  
Type  
Description  
Comments  
Read/Write  
Read/Write  
Command: Written once per frame to initiate transmit.  
Configuration: Written at setup and used to determine  
what frames will be transmitted and received and what  
events will cause interrupts.  
CTL  
Read/Write  
Control: Written at setup and used to determine what  
frames will be transmitted and received and how the physi-  
cal interface will be configured.  
Event  
ST  
Read-only  
Read-only  
Read-only  
Event: Reports the status of transmitted and received  
frames.  
cleared when read  
cleared when read  
Status: Reports information about the configuration of the  
CS8900A.  
Counters: Counts missed receive frames and collisions.  
Provides time domain for locating coax cable faults.  
Table 13. PacketPage Register Types  
Section 4.4.4 on page 49 provides a detailed de- (Register B). Each Interrupt Enable bit corresponds  
scription of the bits in each register.  
to a specific event. If an Interrupt Enable bit is set  
and its corresponding event occurs, the CS8900A  
generates an interrupt to the host processor.  
4.4.3.1 Act-Once Bits  
There are four bits that cause the CS8900A to take  
a certain action only once when set. These "Act-  
Once" bits are: Skip_1 (Register 3, RxCFG, Bit 6),  
RESET (Register 15, SelfCTL, Bit 6), ResetRxD-  
MA (Register 17, BusCTL, Bit 6), and SWint-X  
(Register B, BufCFG, Bit 6). To cause the action  
again, the host must set the bit again. Act-Once bits  
are always read as clear.  
The bits that report when various events occur are  
located in three Event registers and two counters.  
The Event registers are RxEvent (Register 4), Tx-  
Event (Register 8), and BufEvent (Register C). The  
counters are RxMISS (Register 10) and TxCOL  
(Register 12). Each Interrupt Enable bit and its as-  
sociated Event are identified in Table 14.  
An Event bit will be set whenever the specified  
event happens, whether or not the associated Inter-  
rupt Enable bit is set. All Event registers are cleared  
upon read-out by the host.  
4.4.3.2 Temporal Bits  
Temporal bits are bits that are set and cleared by the  
CS8900A without intervention of the host proces-  
sor. This includes all status bits in the three status  
registers (Register 14, LineST; Register 16,  
SelfST; and, Register 18, BusST), the RxDest bit  
(Register C, BufEvent, Bit F), and the Rx128 bit  
4.4.3.4 Accept Bits  
There are nine Accept bits located in the RxCTL  
register (Register 5), each of which is followed by  
(Register C, BufEvent, Bit B). Like all Event bits, the suffix A. Accept bits indicate which types of  
RxDest and Rx128 are cleared when read by the  
host.  
frames will be accepted by the CS8900A. (A frame  
is said to be "accepted" by the CS8900A when the  
frame data are placed in either on-chip memory, or  
in host memory by DMA.) Four of these bits have  
corresponding Interrupt Enable (iE) bits. An Ac-  
cept bit and an Interrupt Enable bit are independent  
4.4.3.3 Interrupt Enable Bits and Events  
Interrupt Enable bits end with the suffix iE and are  
located in three Configuration registers: RxCFG  
(Register 3), TxCFG (Register 7), and BufCFG  
CIRRUS LOGIC PRODUCT DATA SHEET  
48  
DS271PP3  
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