CS8900A
Crystal LAN™ ISA Ethernet Controller
4.4.23 Register 1C: AUI Time Domain Reflectometer
(Read-only, Address: PacketPage base + 013Ch)
7
6
5
4
3
2
1
9
0
8
AUI Delay
011100
F
E
D
C
B
A
AUI Delay
The TDR counter (Bits 6 through F) is a time domain reflectometer useful in locating cable faults in 10BASE-2 and
10BASE-5 coax networks. It counts at a 10 MHz rate from the beginning of transmission on the AUI to when a col-
lision or Loss-of-Carrier error occurs. The TDR counter is cleared when read.
011100
These bits provide an internal address used by the CS8900A to identify this as the Bus Status
Register. When reading this register, these bits will be 011100, where the LSB corresponds to
Bit 0.
AUI-Delay
The upper ten bits contains the number of 10 MHz clock periods between the beginning of
transmission on the AUI to when a collision or Loss-of-Carrier error occurs.
Reset value is: 0000 0000 0001 1100
CIRRUS LOGIC PRODUCT DATA SHEET
70
DS271PP3
CIRRUS [ CIRRUS LOGIC ]
