CS8900A
Crystal LAN™ ISA Ethernet Controller
4.4.20 Register 17: Bus Control
(BusCTL, Read/Write, Address: PacketPage base + 0116h)
7
6
5
4
3
2
1
0
Reset RxDMA
010111
F
E
D
C
B
A
9
8
EnableIRQ
RxDMA size IOCH RDYE
DMABurst
MemoryE
UseSA
DMAextend
BusCTL controls the operation of the ISA-bus interface.
010111
These bits provide an internal address used by the CS8900A to identify this as the Bus Control
Register.
ResetRxDMA
When set, the RxDMA offset pointer at PacketPage base + 0026h is reset to zero. When the
host sets this bit, the CS8900A does the following:
1.Terminates the current receive DMA activity, if any.
2.Clears all internal receive buffers.
3.Zeroes the RxDMA offset pointer.
DMAextend
UseSA
When set, DMARQx goes inactive on the falling edge of IORN instead of the rising edge of
IORN-1. See Switching Characteristics, DMA Read, tDMAR5. Setting this bit also enables single
transfer mode DMA. Normal operation is demand mode DMA in which DMACKx cannot deas-
sert until after DMARQx deasserts, i.e. until a full ethernet frame is transferred. Single transfer
mode allows DMACKx to deassert between each DMA read.
When set, the MEMCS16 pin goes low whenever the address on SA bus [12..19] match the
CS8900A’s assigned Memory base address and the CHIPSEL pin is low (internal address de-
code).
When clear, MEMCS16 is driven low whenever CHIPSEL goes low. (external address decode).
see Section 4.9 on page 74.
For MEMCS16 pin to be enabled, the CS8900A must be in Memory Mode with the MemoryE
bit (Register 17, BusCTL, Bit A) set.
MemoryE
DMABurst
When set, the CS8900A may operate in Memory Mode. When clear, Memory Mode is disabled.
I/O Mode is always enabled.
When clear, the CS8900A performs continuous DMA until the receive frame is completely
transferred from the CS8900A to host memory. When set, each DMA access is limited to 28us,
after which time the CS8900A gives up the bus for 1.3us before making a new DMA request.
IOCHRDYE
When set, the CS8900A does not use the IOCHRDY output pin, and the pin is always high-im-
pedance. This allows external pull-up to force the output high. When clear, the CS8900A drives
IOCHRDY low to request additional time during I/O Read and Memory Read cycles. IOCHRDY
does not affect I/O Write, Memory Write, nor DMA Read.
RxDMAsize
EnableRQ
This bit determines the size of the receive DMA buffer (located in host memory). When set, the
DMA buffer size is 64 Kbytes. When clear, it is 16 Kbytes.
When set, the CS8900A will generate an interrupt in response to an interrupt event
(Section 5.1). When cleared, the CS8900A will not generate any interrupts.
After reset, if no EEPROM is found by the CS8900A, then the register has the following initial state. If an EEPROM
is found, then the register’s initial value may be set by the EEPROM. See Section 3.3 on page 19.
Reset value is: 0000 0000 0001 0111
CIRRUS LOGIC PRODUCT DATA SHEET
DS271PP3
67
CIRRUS [ CIRRUS LOGIC ]
