CS8900A
Crystal LAN™ ISA Ethernet Controller
Failure to observe these three rules may cause data
corruption.
all of the CS8900A’s registers can be accessed di-
rectly.
In Memory Mode, the CS8900A supports Standard
or Ready Bus cycles without introducing additional
wait states.
4.8.1 Transferring Odd-Byte-Aligned Data
Some applications gather transmit data from more
than one section of host memory. The boundary be-
tween the various memory locations may be either Memory moves can use MOVD (double-word
even- or odd-byte aligned. When such a boundary
is odd-byte aligned, the host should transfer the last
transfers) as long as the CS8900A’s memory base
address is on a double word boundary. Since 286
byte of the first block to an even address, followed processors don’t support the MOVD instruction,
by the first byte of the second block to the follow- word and byte transfers must be used with a 286.
ing odd address. It can then resume word transfers.
Description Mnemonic Read/Write
Location:
PocketPage
base +
An example of this is shown in Figure 17.
Word Transfer
Receive
Status
RxStatus Read-only 0400h-0401h
RxLength Read-only 0402h-0403h
RxFrame Read-only starts at 0404h
TxFrame Write-only starts at 0A00h
First Block of Data
Word Transfer
Word Transfer
Byte Transfer
Byte Transfer
Word Transfer
Receive
Length
Receive
Frame
Transmit
Frame
Word Transfer
Second Block of Data
Table 16. Receive/Transmit Memory Locations
Word Transfer
4.9.1 Accesses in Memory Mode
Figure 17. Odd-Byte Aligned Data
The CS8900A allows Read/Write access to the in-
ternal PacketPage memory, and Read access of the
optional Boot PROM. (See Section 3.7 on page 26
for a description of the optional Boot PROM.)
4.8.2 Random Access to CS8900A Memory
The first 118 bytes of a receive frame held in the
CS8900A’s on-chip memory may be randomly ac-
cessed in Memory mode. After the first 118 bytes,
only sequential access of received data is allowed.
Either byte or word access is permitted, as long as
all word accesses are executed to even-byte bound-
aries.
A memory access occurs when all of the following
are true:
•
The address on the ISA System Address bus
(SA0 - SA19) is within the Memory space
range of the CS8900A or Boot PROM.
•
•
The CHIPSEL input pin is low.
4.9 Memory Mode Operation
Either the MEMR pin or the MEMW pin is low.
To configure the CS8900A for Memory Mode, the
PacketPage memory must be mapped into a contig-
uous 4-kbyte block of host memory. The block
must start at an X000h boundary, with the Pack-
etPage base address mapped to X000h. When the
CS8900A comes out of reset, its default configura-
tion is I/O Mode. Once Memory Mode is selected,
4.9.2 Configuring the CS8900A for Memory
Mode
There are two different methods of configuring the
CS8900A for Memory Mode operation. One meth-
od allows the CS8900A's internal memory to be
mapped anywhere within the host system's 24-bit
CIRRUS LOGIC PRODUCT DATA SHEET
74
DS271PP3
CIRRUS [ CIRRUS LOGIC ]
