CS5505/6/7/8
CS5505/6/7/8
5V SWITCHING CHARACTERISTICS (T
= T
to T
VA+, VD+ = 5V ± 10%;
VA- = -5V ± 10%; Input Levels: Logic 0 = 0V, Logic 1 = VD+; C = 50 pF.) (Note 2)
A
MIN
MAX;
L
Parameter
SSC Mode (M/SLP = VD+)
Symbol
Min
Typ
Max
Units
Access Time:
CS Low to SDATA out (DRDY = low)
DRDY falling to MSB (CS = low)
t
-
-
-
2/fclk
3/f
clk
ns
ns
csd1
t
2/f
dfd
clk
SDATA Delay Time:
SCLK Delay Time
Serial Clock (Out)
SCLK falling to next SDATA bit
SDATA MSB bit to SCLK rising
t
-
-
80
250
-
ns
ns
dd1
t
1/f
cd1
clk
Pulse Width High
Pulse Width Low
t
-
-
1/f
1/f
-
-
ns
ns
ph1
clk
clk
t
pl1
Output Float Delay:
CS high to output Hi-Z (Note 16)
SCLK rising to SDATA Hi-Z
t
t
-
-
-
2/f
-
ns
ns
fd1
fd2
clk
1/f
clk
SEC Mode (M/SLP = DGND)
Serial Clock (In)
f
0
-
2.5
MHz
sclk
Serial Clock (In)
Pulse Width High
Pulse Width Low
t
t
200
200
-
-
-
-
ns
ns
ph2
pl2
Access Time:
CS Low to data valid (Note 17)
t
-
60
200
ns
csd2
Maximum Delay time:
(Note 18)
SCLK falling to new SDATA bit
t
-
150
310
ns
dd2
Output Float Delay:
CS high to output Hi-Z (Note 16)
SCLK falling to SDATA Hi-Z
t
t
-
-
60
160
150
300
ns
ns
fd3
fd4
Notes: 16. If CS is returned high before all data bits are output, the SDATA and SCLK outputs will complete the
current data bit and then go to high impedance.
17. If CS is activated asynchronously to DRDY, CS will not be recognized if it occurs when DRDY is high
for 2 clock cycles. The propagation delay time may be as great as 2 f
cycles plus 200 ns. To
clk
guarantee proper clocking of SDATA when using asynchronous CS, SCLK(i) should not be taken high
sooner than 2 f + 200 ns after CS goes low.
clk
18. SDATA transitions on the falling edge of SCLK. Note that a rising SCLK must occur to enable the
serial port shifting mechanism before falling edges can be recognized.
DDSS599FF45
99
CIRRUS [ CIRRUS LOGIC ]
