CS5505/6/7/8
CS5505/6/7/8
5V SWITCHING CHARACTERISTICS (T
= T
to T
VA+, VD+ = 5V ± 10%;
MAX;
A
MIN
VA- = -5V ± 10%; Input Levels: Logic 0 = 0V, Logic 1 = VD+; C = 50 pF.) (Note 2)
L
Parameter
Internal Oscillator:
Symbol
Min
Typ
Max
Units
Master Clock Frequency:
-A,B
-S
XIN
or
f
clk
30.0
30.0
30
32.768
32.768
-
53.0
34.0
163
kHz
kHz
kHz
External Clock:
Master Clock Duty Cycle
Rise Times:
40
-
60
%
Any Digital Input
Any Digital Output
(Note 10)
(Note 10)
t
-
-
-
50
1.0
-
rise
µs
ns
Fall Times:
Any Digital Input
Any Digital Output
t
-
-
-
20
1.0
-
fall
µs
ns
Start-Up
Power-On Reset Period
Oscillator Start-up Time
Wake-up Period
(Note 11)
t
-
-
-
10
-
-
-
ms
ms
s
res
XTAL=32.768 kHz (Note 12)
(Note 13)
t
500
osu
t
1800/f
wup
clk
clk
Calibration
CONV Pulse Width (CAL = 1)
(Note 14)
t
100
-
-
-
ns
ns
s
ccw
CONV and CAL High to Start of Calibration
Start of Calibration to End of Calibration
Conversion
t
t
-
-
2/f
scl
cal
clk+200
3246/f
-
Set Up Time
A0, A1 to CONV High
A0, A1 after CONV High
t
50
100
100
-
-
-
-
-
ns
ns
ns
ns
s
sac
Hold Time
t
-
hca
CONV Pulse Width
t
t
-
cpw
CONV High to Start of Conversion
t
-
2/f +200
clk
scn
bus
buh
Set Up Time
BP/UP stable prior to DRDY falling
BP/UP stable after DRDY falls
(Note 15)
Notes: 10. Specified using 10% and 90% points on waveform of interest.
82/f
-
-
-
-
-
clk
Hold Time
t
0
-
ns
s
Start of Conversion to End of Conversion
t
1624/f
con
clk
11. An internal power-on-reset is activated whenever power is applied to the device, or when coming out
of a SLEEP state.
12. Oscillator start-up time varies with the crystal parameters. This specification does not apply when
using an external clock source.
13. The wake-up period begins once the oscillator starts;
or when using an external f , after the power-on reset time elapses.
clk
14. Calibration can also be initiated by pulsing CAL high while CONV=1.
15. Conversion time will be 1622/f
if CONV remains high continuously.
clk
66
DDSS5599FF54
CIRRUS [ CIRRUS LOGIC ]
