CS5505/6/7/8
CS5505/6/7/8
3.3V SWITCHING CHARACTERISTICS (T
= T
to T VA+ = 5V ± 10%; VD+ = 3.3V ±
MAX
L
A
MIN
5%; VA- = -5V ± 10%; Input Levels: Logic 0 = 0V, Logic 1 = VD+; C = 50 pF.) (Note 2)
Parameter
SSC Mode (M/SLP = VD+)
Symbol
Min
Typ
Max
Units
Access Time:
CS Low to SDATA out (DRDY = low)
DRDY falling to MSB (CS = low)
t
-
-
-
2/fclk
3/f
clk
ns
ns
csd1
t
2/f
dfd
clk
SDATA Delay Time:
SCLK Delay Time
Serial Clock (Out)
SCLK falling to next SDATA bit
SDATA MSB bit to SCLK rising
t
-
-
265
400
-
ns
ns
dd1
t
1/f
cd1
clk
Pulse Width High
Pulse Width Low
t
-
-
1/f
1/f
-
-
ns
ns
ph1
clk
clk
t
pl1
Output Float Delay:
CS high to output Hi-Z (Note 16)
SCLK rising to SDATA Hi-Z
t
t
-
-
-
2/f
-
ns
ns
fd1
fd2
clk
1/f
clk
SEC Mode (M/SLP = DGND)
Serial Clock (In)
f
0
-
1.25
MHz
sclk
Serial Clock (In)
Pulse Width High
Pulse Width Low
t
t
200
200
-
-
-
-
ns
ns
ph2
pl2
Access Time:
CS Low to data valid (Note 17)
t
-
100
200
ns
csd2
Maximum Delay time:
(Note 18)
SCLK falling to new SDATA bit
t
dd2
-
400
600
ns
Output Float Delay:
CS high to output Hi-Z (Note 16)
SCLK falling to SDATA Hi-Z
t
t
-
-
70
320
150
500
ns
ns
fd3
fd4
1100
DDSS5599FF54
CIRRUS [ CIRRUS LOGIC ]
