CS5330A/31A
SCLK output
LRCK output
SDATA
SCLK output
LRCK output
SDATA
t
t
t
mslr
sdo
mslr
t
sdo
SCLK to SDATA LRCK - MASTER mode (CS5331A)
SCLK to SDATA LRCK - MASTER mode (CS5330A)
t
t
t
t
t
t
t
t
slr1 slr2
slr1 slr2
sclkl sclkh
sclkl sclkh
SCLK input
SCLK input
(SLAVE mode)
(SLAVE mode)
t
t
sclkw
sclkw
LRCK input
LRCK input
(SLAVE mode)
(SLAVE mode)
t
t
t
lrdss
dss
dss
MSB
MSB-1
MSB-2
MSB
MSB-1
SDATA
SDATA
SCLK to LRCK & SDATA - SLAVE mode (CS5330A)
SCLK to LRCK & SDATA - SLAVE mode (CS5331A)
+5V
Analog
+
µ
µ
F
10
F
0.1
7
VA+
Audio Data
Processor
µ
.47 F
Ω
Ω
150
150
8
AINL
AINR
**
µ
.01 F
Analog
Input
Circuits
Ω
Ω
Ω
Ω
1 k
1 k
1 k
1 k
4
2
3
1
MCLK
SCLK
CS5330A
CS5331A
Timing
Logic
&
µ
.47 F
5
LRCK
Clock
**
SDATA
µ
.01 F
Ω
47 k
*
AGND
6
Required for Master mode only
*
Optional if analog input circuits biased
to within ± 5% of CS5330A/CS5331A
nominal input bias voltage
**
Figure 1. Typical Connection Diagram
8
DS138F5
CIRRUS [ CIRRUS LOGIC ]
