CS5330A/31A
USER: Apply Power
IniltiPaow-eDrown
USER: AppMlCyLK
MasterMode
MasterMode
SlaveMode
Master/Slave
Decision
SlaveMode
PowerDown
PowerDown
USER: AppMlCyLK
andLRCK
MCLK/LRCK Ratoi
MCLK/LRCK Ratoi
is256xonly
Determinaotni
256/384/512
USER: Rmeove
MCLK
USER: Rmeove
MCLK,LRCK oBroth
Iniltiziaatoin
Iniltiziaatoin
-Highpassfiltersettgin
-SDATAmute realsed
-Highpassfiltersettgisn
-SDATAmute realsed
DigitlaOutput
isgenerated
DigitlaOutput
isGenerated
Figure 4. CS5330A/31A Initialization and Power-Down Sequence
The CS5330A and CS5331A have a Power-Down mode wherein typical consumption drops to 0.5 mW.
This is initiated when a loss of clock is detected on either the LRCK or MCLK pins in Slave Mode, or the
MCLK pin in Master Mode. The initialization sequence will begin when MCLK, and LRCK for slave mode,
are restored. In slave mode power-down, the CS5330A and CS5331A will adapt to changes in
MCLK/LRCK frequency ratio during the initialization sequence. It is recommended that clocks not be ap-
plied to the device prior to power supply settling. A reset circuit may be implemented by gating the MCLK
signal.
3.1.10 Grounding and Power Supply Decoupling
As with any high resolution converter, the ADC requires careful attention to power supply and grounding
arrangements if its potential performance is to be realized. Figure 1 shows the recommended power ar-
rangements with VA+ connected to a clean +5V supply. Decoupling capacitors should be as near to the
ADC as possible, with the low value ceramic capacitor being the nearest. To minimize digital noise, con-
nect the ADC digital outputs only to CMOS inputs. The printed circuit board layout should have separate
analog and digital regions and ground planes. An evaluation board, CDB5330A or CDB5331A, is avail-
able which demonstrates the optimum layout and power supply arrangements, as well as allowing fast
evaluation of the CS5330A and CS5331A.
12
DS138F5
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