CS5330A/31A
SWITCHING CHARACTERISTICS
(Inputs: Logic 0 = 0V, Logic 1 = VA+; CL = 20 pF) Switching characteristics are guaranteed by characterization.
Parameter
Symbol
Fs
tclkw
tclkl
tclkh
tclkw
tclkl
tclkh
tclkw
tclkl
Min
2
Typ
Max
50
Unit
kHz
ns
-
-
-
-
-
-
-
-
-
-
Output Sample Rate
MCLK Period
MCLK Low
78
31
31
52
20
20
39
13
13
1000
1000
1000
1000
1000
1000
1000
1000
1000
MCLK/LRCK = 256
MCLK/LRCK = 256
MCLK/LRCK = 256
MCLK/LRCK = 384
MCLK/LRCK = 384
MCLK/LRCK = 384
MCLK/LRCK = 512
MCLK/LRCK = 512
MCLK/LRCK = 512
ns
ns
MCLK High
ns
MCLK Period
MCLK Low
ns
ns
MCLK High
ns
MCLK Period
MCLK Low
ns
tclkh
ns
MCLK High
MASTER MODE
SCLK falling to LRCK
tmslr
tsdo
-10
-10
-
-
-
10
35
-
ns
ns
%
SCLK falling to SDATA valid
SCLK Duty cycle
50
SLAVE MODE
25
50
-
75
%
ns
ns
ns
ns
ns
ns
ns
LRCK duty cycle
tclkw
tclkl
tclkh
tdss
tlrdss
tslr1
tslr2
(Note 9)
-
SCLK Period
(Note 10)
-
-
SCLK Pulse Width Low
SCLK Pulse Width High
SCLK falling to SDATA valid
LRCK edge to MSB valid
SCLK rising to LRCK edge delay
LRCK edge to rising SCLK setup time
20
-
-
-
-
(Note 11)
-
-
(Note 11)
20
-
-
-
(Note 11)
-
9.
1
64 F
s
10.
11.
1
- 15 ns
+ 5 ns
128 F
s
s
1
256 F
DS138F5
7
CIRRUS [ CIRRUS LOGIC ]
