CS5330A/31A
1. PIN DESCRIPTIONS
1
2
3
4
8
7
6
5
AINL
VA+
LEFT ANALOG INPUT
SERIAL DATA OUTPUT
SERIAL DATA CLOCK
SDATA
SCLK
ANALOG POWER
AGND
AINR
ANALOG GROUND
RIGHT ANALOG INPUT
LEFT/RIGHT CLOCK
MASTER CLOCK
LRCK
MCLK
#
Pin Name
Pin Description
Audio Serial Data Output (Output) - Two’s complement MSB-first serial data is output on this
pin. A 47 kΩ resistor on this pin will place the CS5330A/31A into Master Mode.
1
SDATA
Serial Data Clock (Input/Output) - SCLK is an input clock at any frequency from 32x to 64x the
output word rate. SCLK can also be an output clock at 64x if in the Master Mode. Data is
clocked out on the falling edge of SCLK.
2
3
SCLK
LRCK
Left/Right Clock (Input/Output) - LRCK selects the left or right channel for output on SDATA.
The LRCK frequency must be at the output sample rate. LRCK is an output clock if in Master
Mode. Although the outputs of each channel are transmitted at different times, the two words in
an LRCK cycle represent simultaneously sampled analog inputs.
Master Clock Input (Input) - Source for the delta-sigma modulator sampling and digital filter
clock. Sample rates and digital filter characteristics scale to the MCLK frequency.
4
5
MCLK
AINR
Analog Right Channel Input (Input) - Analog input for the right channel. Typically 4 Vpp for a
full-scale input signal.
AGND
VA+
6
7
Analog Ground (Input) - Analog ground reference.
Positive Analog Power (Input) - Positive analog supply (Nominally +5 V).
Analog Left Channel Input (Input) - Analog input for the left channel. Typically 4 Vpp for a full-
scale input signal.
8
AINL
DS138F5
3
CIRRUS [ CIRRUS LOGIC ]
