CS5101A CS5102A
SWITCHING CHARACTERISTICS (Continued)
Parameter
Symbol
Min
Typ
Max
Units
PDT and RBT Modes
SCLK Input Pulse Period
t
200
50
50
-
-
-
-
ns
ns
ns
ns
ns
ns
sclk
SCLK Input Pulse Width Low
SCLK Input Pulse Width High
SCLK Input Falling to SDATA Valid
t
-
sclkl
t
-
-
sclkh
t
100
140
65
150
230
125
dss
dhs
HOLD Falling to SDATA Valid
TRK1, TRK2 Falling to SDATA Valid
FRN and SSC Modes
PDT Mode
(Note 30)
t
-
t
-
dts
SCLK Output Pulse Width Low
SCLK Output Pulse Width High
SDATA Valid Before Rising SCLK
SDATA Valid After Rising SCLK
SDL Falling to 1st Rising SCLK
Last Rising SCLK to SDL Rising
t
-
-
2t
2t
-
t
t
slkl
clk
clk
t
-
slkh
clk
clk
t
2t -100
clk
-
-
ns
ns
ns
ss
sh
t
2t -100
clk
-
-
t
-
2t
clk
-
rsclk
CS5101A
CS5102A
t
-
-
2t
clk
2tclk+165
2t +200
clk
ns
ns
rsdl
t
rsdl
2tclk
HOLD Falling to 1st Falling SCLK
CH1/2 Edge to 1st Falling SCLK
CS5101A
CS5102A
t
6tclk
-
-
8t +165
8t +200
clk
ns
ns
hfs
clk
6t
clk
thfs
t
-
7tclk
-
t
clk
chfs
Note: 30. Only valid for TRK1, TRK2 falling when SCLK is low. If SCLK is high when TRK1, TRK2 falls, then
SDATA is valid t time after the next falling SCLK.
dss
DIGITAL CHARACTERISTICS (T = T to T ; VA+, VD+ = 5V ± 10%; VA-,
A
min
max
VD- = 5V ± 10%)
Parameter
Symbol
Min
Typ
Max
Units
Calibration Memory Retention
(Note 31)
V
MR
2.0
-
-
V
Power Supply Voltage VA+ and VD+
High-Level Input Voltage
Low-Level Input Voltage
High-Level Output Voltage
Low-Level Output Voltage
Input Leakage Current
V
2.0
-
-
-
0.8
-
V
V
IH
V
-
IL
(Note 32)
= 1.6 mA
V
OH
(VD+)-1.0
-
V
I
V
OL
I
in
-
-
-
-
0.4
10
-
V
OUT
-
µA
pF
Digital Output Pin Capacitance
C
out
9
Notes: 31. VA- and VD- can be any value from zero to -5V for memory retention. Neither VA- or VD- should be
allowed to go positive. AIN1, AIN2 or VREF must not be greater than VA+ or VD+.
This parameter is guaranteed by characterization.
32. I
= -100 µA. This specification guarantees TTL compatibility (V
= 2.4V @ Iout = -40 µA).
OH
OUT
DS45F2
9
CIRRUS [ CIRRUS LOGIC ]
