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CS5101A-JL16 参数 Datasheet PDF下载

CS5101A-JL16图片预览
型号: CS5101A-JL16
PDF下载: 下载PDF文件 查看货源
内容描述: 16位, 100kHz的/ 20kHz的A / D转换器 [16-Bit, 100kHz/ 20kHz A/D Converters]
分类和应用: 转换器
文件页数/大小: 40 页 / 461 K
品牌: CIRRUS [ CIRRUS LOGIC ]
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CS5101A CS5102A  
Calibration  
the track mode. After allowing a short time for  
acquisition, the device will be ready for another  
conversion.  
The ability of the CS5101A or the CS5102A to  
convert accurately to 16-bits clearly depends on  
the accuracy of its comparator and DAC. Each  
device utilizes an "auto-zeroing" scheme to null  
errors introduced by the comparator. All offsets  
are stored on the capacitor array while in the  
track mode and are effectively subtracted from  
the input signal when a conversion is initiated.  
Auto-zeroing enhances power supply rejection at  
frequencies well below the conversion rate.  
In contrast to systems with separate track-and-  
holds and A/D converters, a sampling clock can  
simply be connected to the HOLD input. The  
duty cycle of this clock is not critical. The HOLD  
input is latched internally by the master clock, so  
it need only remain low for 1/f + 20 ns, but no  
clk  
longer than the minimum conversion time minus  
two master clocks or an additional conversion cy-  
cle will be initiated with inadequate time for  
acquisition. In Free Run mode, SCKMOD =  
OUTMOD = 0, the device will convert at a rate  
of CLKIN/80, and the HOLD input is ignored.  
To achieve 16-bit accuracy from the DAC, the  
CS5101A and CS5102A use a novel self-calibra-  
tion scheme. Each bit capacitor shown in  
Figure 1 actually consists of several capacitors in  
parallel which can be manipulated to adjust the  
overall bit weight. An on-chip micro controller  
precisely adjusts each capacitor with a resolution  
of 18 bits.  
As with any high-resolution A-to-D system, it is  
recommended that sampling is synchronized to  
the master system clock in order to minimize the  
effects of clock feedthrough. However, the  
CS5101A and CS5102A may be operated entirely  
asynchronous to the master clock if necessary.  
The CS5101A and CS5102A should be reset  
upon power-up, thus initiating a calibration cycle.  
The device then stores its calibration coefficients  
in on-chip SRAM. When the CS5101A and  
CS5102A are in power-down mode (SLEEP  
low), they retain the calibration coefficients in  
memory, and need not be recalibrated when nor-  
mal operation is resumed.  
Tracking the Input  
Upon completing a conversion cycle the  
CS5101A and CS5102A immediately return to  
the track mode. The CH1/2 pin directly controls  
the input switch, and therefore directly deter-  
mines which channel will be tracked. Ideally, the  
CH1/2 pin should be switched during the conver-  
sion cycle, thereby nullifying the input mux  
switching time, and guaranteeing a stable input at  
the start of acquisition. If, however, the CH1/2  
control is changed during the acquisition phase,  
adequate coarse charge and fine charge time must  
be allowed before initiating conversion.  
OPERATION OVERVIEW  
Monolithic design and inherent sampling archi-  
tecture make the CS5101A and CS5102A  
extremely easy to use.  
Initiating Conversions  
When the CS5101A or the CS5102A enters track-  
ing mode, it uses an internal input buffer  
amplifier to provide the bulk of the charge on the  
capacitor array (coarse-charge), thereby reducing  
the current load on the external analog circuitry.  
Coarse-charge is internally initiated for 6 clock  
cycles at the end of every conversion. The buffer  
A falling transition on the HOLD pin places the  
input in the hold mode and initiates a conversion  
cycle. The charge is trapped on the capacitor ar-  
ray the instant HOLD goes low. The device will  
complete conversion of the sample within 66  
master clock cycles, then automatically return to  
DS45F2  
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