CS5102A
SWITCHING CHARACTERISTICS (T = T
to T
;
A
MIN
MAX
VA+, VD+ = 5V ± 10%; VA-, VD- = -5V ± 10%; Inputs: Logic 0 = 0V, Logic 1 = VD+; C = 50 pF)
L
Parameter
Symbol
Min
Typ
Max
Units
CLKIN Period
(Note 18,24)
t
0.5
-
10
clk
µs
ns
CLKIN Low Time
CLKIN High Time
Crystal Frequency
t
200
-
-
clkl
t
200
-
-
ns
clkh
(Note 24, 25)
(Note 26)
f
0.9
1.6
2.0
MHz
ms
ns
xtal
SLEEP Rising to Oscillator Stable
RST Pulse Width
-
-
20
-
-
-
-
-
t
150
-
rst
RST to STBY Falling
t
-
-
-
-
-
100
ns
drrs
RST Rising to STBY Rising
CH1/2 Edge to TRK1, TRK2 Rising
CH1/2 Edge to TRK1, TRK2 Falling
HOLD to SSH Falling
t
cal
2,882,040
t
clk
(Note 27)
(Note 27)
(Note 28)
(Note 28)
(Note 28)
(Note 29)
(Note 28)
(Note 29)
t
t
t
t
80
ns
drsh1
dfsh4
dfsh2
dfsh1
-
68t +260 ns
clk
60
ns
HOLD to TRK1, TRK2, Falling
HOLD to TRK1, TRK2, SSH Rising
HOLD Pulse Width
66t
-
-
68t +260 ns
clk
clk
t
120
-
63t
64t
ns
ns
ns
ns
drsh
t
t
1t +20
clk
-
-
-
hold
dhlri
clk
clk
HOLD to CH1/2 Edge
15
55
HOLD Falling to CLKIN Falling
t
hcf
1tclk+10
Note: 24. Minimum CLKIN period is 0.625 µs in FRN mode (20 kHz sample rate). At temperatures >+85 °C,
and with clock frequencies <1.6 MHz, analog performance may be degraded.
25. External loading capacitors are required to allow the crystal to oscillate. Maximum crystal frequency
is 1.6 MHz in FRN mode (20 kHz sample rate).
26. With a 2.0 MHz crystal, two 33 pF loading capacitors and a 10 MΩ parallel resistor (see Figure 8).
27. These times are for FRN mode.
28. SSH only works correctly if HOLD falling edge is within +15 to +30 ns of CH1/2 edge or if CH1/2 edge
occurs after HOLD rises to 64 t after HOLD has fallen. These times are for PDT and RBT modes.
clk
29. When HOLD goes low, the analog sample is captured immediately. To start conversion, HOLD must
be latched by a falling edge of CLKIN. Conversion will begin on the next rising edge of CLKIN
after HOLD is latched. If HOLD is operated synchronous to CLKIN, the HOLD pulse width may be as
narrow as 150 ns for all CLKIN frequencies if CLKIN falls 55 ns after HOLD falls. This
ensures that the HOLD pulse will meet the minimum specification for t
.
hcf
DS45F2
7
CIRRUS [ CIRRUS LOGIC ]
