CS4923/4/5/6/7/8/9
SWITCHING CHARACTERISTICS—INTEL® HOST MODE
(TA = 25 °C; VA, VD = 3.3 V ±5%; Inputs: Logic 0 = DGND, Logic 1 = VD, CL = 20 pF)
Parameter
Symbol
Min
Max
Unit
Tias
5
-
ns
Address setup before CS and RD low or CS and WR low
Address hold time after CS and RD low or CS and WR low
Delay between RD then CS low or CS then RD low
Data valid after CS and RD low
Tiah
Ticdr
Tidd
5
-
∞
20
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
0
-
Tirpw
Tidhr
Tidis
DCLK + 10
CS and RD low for read
(Note 1)
5
-
Data hold time after CS or RD high
Data high-Z after CS or RD high
-
15
-
(Note 2)
(Note 1)
(Note 1)
Tird
2*DCLK + 10
2*DCLK + 10
0
CS or RD high to CS and RD low for next read
CS or RD high to CS and WR low for next write
Delay between WR then CS low or CS then WR low
Data setup before CS or WR high
Tirdtw
Ticdw
Tidsu
Tiwpw
Tidhw
Tiwtrd
Tiwd
-
∞
-
20
DCLK + 10
5
-
CS and WR low for write
(Note 1)
-
Data hold after CS or WR high
2*DCLK + 10
2*DCLK + 10
-
CS or WR high to CS and RD low for next read
CS or WR high to CS and WR low for next write
(Note 1)
(Note 1)
-
Notes: 1. Certain timing parameters are normalized to the DSP clock, DCLK, in nanoseconds. The DSP clock can
be defined as follows:
External CLKIN Mode:
DCLK == CLKIN/3 before and during boot
DCLK == CLKIN after boot
Internal Clock Mode:
DCLK == 10MHz before and during boot, i.e. DCLK == 100ns
DCLK == 60 MHz after boot, i.e. DCLK == 16.7ns (this speed may depend on CLKIN, please see
CS4923/4/5/6/7/8/9 Hardware User’s Guide for more information)
2. This specification is characterized but not production tested.
8
DS262F2
CIRRUS [ CIRRUS LOGIC ]
