CS4923/4/5/6/7/8/9
SWITCHING CHARACTERISTICS—SPI CONTROL PORT
(TA = 25 °C; VA, VD = 3.3 V ±5%; Inputs: Logic 0 = DGND, Logic 1 = VD, CL = 20 pF)
Parameter
Symbol
Min
Max
Units
SCCLK clock frequency
CS falling to SCCLK rising
Rise time of SCCLK line
Fall time of SCCLK lines
SCCLK low time
(Note 5)
fsck
-
2000
kHz
tcss
tr
20
-
-
50
50
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
(Note 11)
(Note 11)
tf
-
tscl
150
150
50
50
-
SCCLK high time
tsch
tcdisu
tcdih
tscdov
tscrh
trr
-
Setup time SCDIN to SCCLK rising
Hold time SCCLK rising to SCDIN
Transition time from SCCLK to SCDOUT valid
Time from SCCLK rising to INTREQ rising
Rise time for INTREQ
-
(Note 6)
(Note 7)
(Note 8)
(Note 8)
-
40
200
-
-
(Note
10)
Hold time for INTREQ from SCCLK rising
Time from SCCLK falling to CS rising
High time between active CS
(Note 9, 11)
tscrl
tsccsh
tcsht
0
-
-
ns
ns
ns
ns
20
200
-
Time from CS rising to SCDOUT high-Z
(Note 11)
tcscdo
10
Notes: 5. The specification fsck indicates the maximum speed of the hardware. The system designer should be
aware that the actual maximum speed of the communication port may be limited by the software. The
relevant application code user’s manual should be consulted for the software speed limitations.
6. Data must be held for sufficient time to bridge the 50 ns transition time of SCCLK.
7. SCDOUT should not be sampled during this time period.
8. INTREQ goes high only if there is no data to be read from the DSP at the rising edge of SCCLK for the
second-to-last bit of the last byte of data during a read operation as shown.
9. If INTREQ goes high as indicated in Note 8, then INTREQ is guaranteed to remain high until the next
rising edge of SCCLK. If there is more data to be read at this time, INTREQ goes active low again. Treat
this condition as a new read transaction. Raise chip select to end the current read transaction and then
drop it, followed by the 7-bit address and the R/W bit (set to 1 for a read) to start a new read transaction.
10. With a 4.7k Ohm pull-up resistor this value is typically 215ns. As this pin is open drain adjusting the pull
up value will affect the rise time.
11. This time is by design and not tested.
12
DS262F2
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