CS4349
SWITCHING CHARACTERISTICS - CONTROL PORT - SPI FORMAT
Inputs: Logic 0 = GND; Logic 1 = VLC; C = 20 pF.
L
Parameter
CCLK Clock Frequency
Symbol
Min
-
Max
Unit
MHz
ns
f
6
sclk
RST Rising Edge to CS Falling
CCLK Edge to CS Falling (Note 10)
CS High Time Between Transmissions
CS Falling to CCLK Edge
t
500
500
1.0
20
66
66
40
15
-
-
srs
t
-
ns
spi
t
-
µs
csh
t
-
-
ns
css
CCLK Low Time
t
ns
scl
sch
dsu
CCLK High Time
t
-
ns
CDIN to CCLK Rising Setup Time
CCLK Rising to DATA Hold Time (Note 11)
Rise Time of CCLK and CDIN (Note 12)
Fall Time of CCLK and CDIN (Note 12)
Transition Time from CCLK to CDOUT Valid (Note 13)
Time from CS rising to CDOUT High-Z
t
-
ns
t
-
ns
dh
t
100
100
100
100
ns
r2
t
-
ns
f2
t
-
ns
scdov
cscdo
t
-
ns
Notes: 10. t only needed before first falling edge of CS after RST rising edge. t = 0 at all other times.
spi
spi
11. Data must be held for sufficient time to bridge the transition time of CCLK.
12. For F < 1 MHz.
SCK
13. CDOUT should not be sampled during this time.
RST
CS
t
t
srs
t
t
t
spi css
scl
sch
t
csh
CCLK
t
t
r2
f2
CDIN
t
t
dsu
dh
Hi-Impedance
CDOUT
t
t
t
cscdo
scdov
scdov
Figure 9. Control Port Timing - SPI Mode
DS782F1
15
CIRRUS [ CIRRUS LOGIC ]
