CS4349
.
tlrckh
LRCK
(input)
LRCK
(Input)
tlckd
tlcks
tsckh
tsckl
tfsh
tfss
tsckh
tsckl
SCLK
(input)
SCLK
(Input)
tds
tdh
tds
tdh
SDIN
SDIN
MSB
MSB-1
MSB
MSB-1
(input)
(Input)
Figure 6. Serial Port Timing, Non-TDM Mode
Figure 7. Serial Port Timing, TDM Mode
SWITCHING CHARACTERISTICS - CONTROL PORT - I²C FORMAT
Inputs: Logic 0 = GND; Logic 1 = VLC; C = 20 pF.
L
Parameter
Symbol
fscl
Min
-
Max
100
-
Unit
kHz
ns
SCL Clock Frequency
tirs
500
RST Rising Edge to Start
Bus Free Time Between Transmissions
Start Condition Hold Time (prior to first clock pulse)
Clock Low time
tbuf
thdst
tlow
4.7
4.0
4.7
4.0
4.7
0
-
µs
µs
µs
µs
µs
µs
ns
µs
ns
µs
ns
-
-
Clock High Time
thigh
tsust
thdd
-
Setup Time for Repeated Start Condition
SDA Hold Time from SCL Falling (Note 9)
SDA Setup time to SCL Rising
Rise Time of SCL and SDA
-
-
tsud
250
-
-
1
trc, trc
tfc, tfc
tsusp
tack
Fall Time SCL and SDA
-
300
-
Setup Time for Stop Condition
Acknowledge Delay from SCL Falling
4.7
300
1000
Note: 9. Data must be held for sufficient time to bridge the transition time, t , of SCL.
fc
RST
t
irs
Repeated
Stop
Start
Stop
Start
t
t
rd
fd
SDA
SCL
t
t
t
t
t
buf
t
high
hdst
fc
susp
hdst
low
t
t
t
t
t
t
sust
sud
ack
rc
hdd
Figure 8. Control Port Timing - I²C Format
14
DS782F1
CIRRUS [ CIRRUS LOGIC ]
