CS4349
SWITCHING SPECIFICATIONS - SERIAL AUDIO INTERFACE
Inputs: Logic 0 = GND; Logic 1 = VLS; C = 20 pF.
L
Parameters
Symbol
Min
Max
Units
3.14 V ≤ VA ≤ 5.25 V and 1.35 V ≤ VLS ≤ 5.25 V
RMCK Output Frequency (Note )
RMCK Output Duty Cycle
Input Sample Rate
7.680
45
30
60
120
40
1
55.3
55
54
108
216
60
-
MHz
%
Single-Speed Mode
Double-Speed Mode
Quad-Speed Mode
Fs
kHz
LRCK Duty Cycle (Non-TDM Mode)
%
ns
ns
SDIN Setup Time Before SCLK Rising Edge
SDIN Hold Time After SCLK Rising Edge
tds
tdh
1
-
4.75 V ≤ VA ≤ 5.25 V and 3.14 V ≤ VLS ≤ 5.25 V
SCLK Frequency
-
55.3
MHz
ns
SCLK High Time
tsckh
tsckl
6
6
-
-
SCLK Low Time
ns
Non-TDM Mode (refer to Figure 6)
LRCK Edge to SCLK Rising Edge
SCLK Rising Edge to LRCK Edge
TDM Mode (refer to Figure 7)
LRCK High Time
tlcks
tlckd
11
1
-
-
ns
ns
tlrckh
tfsh
tfss
6
3
1
-
-
-
ns
ns
ns
SCLK Rising to LRCK Falling Edge
LRCK Rising Edge to SCLK Rising Edge
3.14 V ≤ VA < 4.75 V or 1.35 V ≤ VLS < 3.14 V
SCLK Frequency
-
27.7
MHz
ns
SCLK High Time
tsckh
tsckl
11
11
-
-
SCLK Low Time
ns
Non-TDM Mode (refer to Figure 6)
LRCK Edge to SCLK Rising Edge
SCLK Rising Edge to LRCK Edge
TDM Mode (refer to Figure 7)
LRCK High Time
tlcks
tlckd
16
1
-
-
ns
ns
tlrckh
tfsh
tfss
25
8
-
-
-
ns
ns
ns
SCLK Rising to LRCK Falling Edge
LRCK Rising Edge to SCLK Rising Edge
1
DS782F1
13