CS4297A
CS4297A
AC ’97 SERIAL PORT TIMING Standard test conditions unless otherwise noted: Tambient = 25° C,
AVdd = 5.0 V, DVdd = 3.3 V; CL = 55 pF load.
Parameter
Symbol
Min
Typ
Max
Unit
RESET Timing
RESET# active low pulse width
RESET# inactive to BIT_CLK start-up delay
1st SYNC active to CODEC READY set
Vdd stable to Reset inactive
Clocks
Trst_low
Trst2clk
Tsync2crd
Tvdd2rst#
1.0
-
-
-
-
-
-
-
µs
µs
µs
µs
40.0
62.5
-
100
BIT_CLK frequency
Fclk
Tclk_period
-
-
12.288
81.4
-
40.7
40.7
48
-
MHz
ns
BIT_CLK period
-
750
45
45
-
BIT_CLK output jitter (depends on XTAL_IN source)
BIT_CLK high pulse width
-
ps
ns
Tclk_high
Tclk_low
Fsync
Tsync_period
Tsync_high
Tsync_low
36
36
-
BIT_CLK low pulse width
ns
SYNC frequency
SYNC period
kHz
µs
µs
-
20.8
1.3
-
SYNC high pulse width
-
-
SYNC low pulse width
-
19.5
-
µs
Data Setup and Hold
Output Propagation delay from rising edge of BIT_CLK
Input setup time from falling edge of BIT_CLK
Input hold time from falling edge of BIT_CLK
Input Signal rise time
Tco
Tisetup
Tihold
Tirise
Tifall
8
10
0
10
-
-
12
-
-
ns
ns
ns
ns
ns
ns
ns
2
-
6
6
6
6
Input Signal fall time
2
2
-
4
4
Output Signal rise time
(Note 4)
(Note 4)
Torise
Tofall
Output Signal fall time
2
Misc. Timing Parameters
End of Slot 2 to BIT_CLK, SDATA_IN low (PR4)
SYNC pulse width (PR4) Warm Reset
SYNC inactive (PR4) to BIT_CLK start-up delay
Setup to trailing edge of RESET# (ATE test mode) (Note 4) Tsetup2rst
Rising edge of RESET# to Hi-Z delay
Ts2_pdown
Tsync_pr4
Tsync2clk
-
1.0
162.8
15
.28
1.0
µs
µs
ns
ns
ns
-
-
-
-
285
-
-
(Note 4)
Toff
-
25
DS318PP6
7
7
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